Comparative study of sub-volt differential difference current conveyors

Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limit their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG)^* technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at ±300 mV supply voltage and 18.5 µW power consumption. The simulation results using 0.18 µm CMOS n-Well process from TSMC show the features of the proposed circuits.     

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700 $\mathrm{\mu }A$ with an input and output impedance of 160 $\Omega$ and 8.55 $\mathrm{G}\Omega$ respectively and high bandwidth of 4.05 $\mathrm{GHz}$. The total power consumption of the proposed current mirror is about 0.84 mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18 $\mathrm{\mu }m$ mixed-mode twill-well technology at a supply voltage of ±0.5 V.     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

In this paper, novel non-conventional techniques,¹ named by the author of this paper “bulk-driven floating-gate (BD-FG)” MOS transistor (MOST) and “bulk-driven quasi-floating-gate (BD-QFG) MOST” for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only ±0.4 V with a rail-to-rail voltage swing capability and total power consumption of mere 10 μW. PSpice simulation results using the 0.18 μm P-well CMOS technology are included to confirm the attractive properties of these new techniques.     

A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell

The paper presents a class-AB flipped voltage follower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/output voltage swing and low output resistance. In the proposed FVF cell, the level shifter increases the input/output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in low output resistance. The proposed FVF cell offers wide input/output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and low output resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.     

Quasi-floating gate MOSFET based low voltage current mirror

This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the design of a low voltage current mirror and highlights its advantages over the floating gate MOSFET (FGMOS). The use of resistive compensation has been shown to enhance the bandwidth of QFGMOS current mirror. The proposed current mirror based on QFGMOS has a current range up to 500 μA with offset of 2.2 nA, input resistance of 235 Ω, output resistance of 117 kΩ, current transfer ratio of 0.98, dissipates 0.83 mW power and exhibits bandwidth of 656 MHz which increases to 1.52 GHz with resistive compensation. The theoretical and simulation results are in good agreement. The workability of the circuits has been verified using PSpice simulation for 0.13 μm technology with a supply voltage of ±0.5 V.     

A new flipped voltage follower with enhanced bandwidth and low output impedance

The paper proposes a flipped voltage follower (FVF) cell with wider bandwidth and lower output impedance as compared to the conventional FVF. These improvements are obtained by adding a resistance in the feedback path of conventional FVF. A current mirror is implemented by using proposed FVF cell to verify the performance improvement. The circuits are designed in TSMC 0.18-µm CMOS technology with 1.5 V supply voltage. The simulation results show that bandwidth extension ratio (BWER) of newly developed FVF is 1.4 without peaking and 1.7 with peaking. The BWERs of the passive-compensated current mirror implemented by using proposed FVF cell are 1.28 without peaking and 1.58 with peaking in the frequency response.     

High frequency flipped voltage follower with improved performance and its application

In this paper a wideband flipped voltage follower (FVF) with low output impedance at high frequency has been proposed. Inductive-peaking-based bandwidth extension technique is employed in the FVF cell. The small signal high-frequency analysis of both conventional and proposed FVF has been done. It is shown in analytical derivation of the proposed FVF that by adding an inductive element in the feedback path, the bandwidth is enhanced. Simulation results show that bandwidth extension ratio (BWER) of proposed FVF is about 2.00, without extra dc power dissipation. A wideband low voltage current mirror has been developed by using proposed FVF in place of conventional FVF and by doing so, BWER of 2.98 has been achieved. The performances of circuits are verified in TSMC 0.18 μm CMOS, BSIM3 and Level 49 technology with 1.5 V power supply and by using Spectre simulator of Cadence.     

Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure

In this paper, a Low Noise Amplifier (LNA) with the current reused topology is proposed for wideband applications. To increase input impedance matching common source with inductive degeneration and RC shunt feedback structure is used. To extend the bandwidth, inductive series peaking technique is utilized. In the next stage, two parallel structure is hired to have a high voltage gain with low power consumption in addition to improve linearity. Also, by using the self-forward-body-bias (SFBB) technique, supply voltage is reduced and as a result power consumption is decreased further. The proposed LNA exhibits the high and flat gain of 14.7–15.4 ​dB, input return loss of less than −11 ​dB and noise figure range of 2.3–4.4 ​dB from 1 ​GHz up to 8 ​GHz. It consumes 5.4 ​mW from a 1.2 ​V power supply. The achieved IIP3 range for the proposed LNA is 0 ​dBm up to +2.7 ​dBm. The proposed LNA occupies 0.45 ​mm² in 0.18-μm CMOS technology.     

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.     

A novel wide band super transistor based voltage feedback current amplifier

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18 μm CMOS technology parameters and supply voltage of ±0.75 V. Simulation results with HSPICE show low THD of ?60 dB at the output signal, very low impedance of 0.6 Ω and 0.2 Ω at the input and feedback ports respectively and high output impedance of 10 MΩ. Moreover it can provide wide ?3 dB bandwidth of 15.5 MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.     

Current mode single-input multi-output MOSFET-only filter

In this paper, a very simple topology of a current mode MOSFET-only filter with single-input and multi-output is proposed. It is very important to emphasize that it is possible to obtain five of the filter functions, namely low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) using the proposed topology without using external passive elements. The core circuit of the proposed filter employs only four MOS transistors; therefore, it occupies very small chip area. It is also possible to adjust the filter gain with the biasing voltage. In addition, the circuit exhibits a very low input impedance and also high output impedances which make it possible for cascading. The MOSFET capacitances which determine the transfer functions are all grounded, so physical capacitances can be used instead of MOSFET parasitic capacitances to operate the filter at very low frequencies. Moreover, proposed filter structure has low supply voltage as 1 V in order to be applicable to low voltage operations. Detailed simulation results, including noise and Monte Carlo analysis, are provided using 0.18 µm TSMC technology parameters to verify the feasibility of the filter circuit.     

An ultra low power,low voltage tailless QFG based differential amplifier with High CMRR,rail to rail operation and enhanced slew rate

This paper proposes a novel tailless ultra low power low voltage high CMRR differential amplifier (D.A.) with rail-to-rail input common mode range (ICMR) based on quasi floating gate (QFG) transistors. For low voltage operation, the tail current source of the conventional D.A. is removed and the resulted lack of CMRR is highly compensated by means of two simple inverters. The required supply voltage is only VGS + VDS_sat (with their usual meanings of symbols) which is one VDS_sat lower than the required supply voltage for the conventional D.A. Unlike the conventional differential amplifier, slew rate (SR) in the proposed one is not limited by the tail current source and is determined by the amplitude of input signals. The principle of operation, small signal analysis and the formula of the most important parameters of the proposed D.A. are presented. HSPICE simulation results using TSMC 0.18 μm CMOS process parameters and ±0.4 V supply voltage are presented which verify the high performance of the proposed scheme. The simulation results show a rail-to-rail operation and 121 dB CMRR for the proposed tailless differential amplifier. The corner case simulation results are also provided which show a robust performance for the proposed structure. Its unity gain bandwidth product is 72.3 MHz that is 2.31 times larger than that of conventional differential amplifier. Positive and negative SRs are improved by a factor of 7.4 and 3.58 times respectively compared to conventional one. It has also an ultra low power dissipation of 6.89 μW.     

Very low input impedance low power current mirror

In this paper a novel low input impedance current mirror/source is proposed. The principle of its operation compared to that of the simple current mirror is discussed. Also are given the comparative simulation results with HSPICE in TSMC 0.18 μm CMOS which verify the theoretical formulation and operation of the proposed structure. Simulation results show an input resistance for the proposed current mirror about 0.006 Ω. This is 4 × 10⁵ times lower than that of the simple one while both working with 1.5 V supply and 50 μA bias current. It consumes only 161 μW and exhibits an excellent current error value of Zero at 55 μA which remains below 0.6% up to 100 μA. Favorably its minimum output voltage is reduced to 0.2 V.     

A very high performance self-biased cascode current mirror for CMOS technology

This paper presents a novel high performance self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This circuit uses super cascode configuration to obtain high output impedance required for high performance of CM. Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM are carried out by Mentor Graphics Eldospice based on TSMC 0.18 μm CMOS technology, for input current range of 0–500 μA. A bandwidth of 2.26 GHz, input and output resistances of 679 Ω and 482 MΩ respectively, are obtained with a single supply voltage of ?1 V.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

Flipped voltage follower based fourth order filter and its application to portable ECG acquisition system

This paper presents the designing of a compact flipped voltage follower (FVF) based fourth order low-pass filter (LPF). The circuit is designed by cascading current-reuse P-FVF and N-FVF biquads operating in sub-threshold region. The circuit attains a cut-off frequency of 206.14 Hz designed for portable ECG acquisition system. The proposed circuit is simulated in 0.13  μm CMOS technology in Cadence environment. The circuit occupies a chip area of 180.310  μm × 552.390  μm i.e. 0.0996 mm². LPF consumes 2.46 nW power with a supply voltage of 0.5 V. It provides a dynamic range of 65.17 dB with input referred noise of 22.214μVrms, HD₃ of 60.3 dB with 50 mVpp 50 Hz frequency. The circuit is compared with state of the art LPFs which provides the best figure of merit and shows enhanced performance in terms of noise, HD3 and dynamic range with lowest supply voltage and technology node.     

Very Low Power, Low Voltage, High Accuracy, and High Performance Current Mirror

A novel low power and low voltage current mirror with a very low current copy error is presented and the principle of its operation is discussed.In this circuit,the gain boosting regulated cascode scheme is used to improve the output resistance,while using inverter as an amplifier.The simulation results with HSPICE in TSMC 0.18 μm CMOS technology are given,which verify the high performance of the proposed structure.Simulation results show an input resistance of 0.014 Ω and an output resistance of 3 GΩ.The current copy error is favorable as low as 0.002％ together with an input (the minimum input voltage of vin,min～ 0.24 V) and an output (the minimum output voltage of vout,min～ 0.16 V) compliances while working with the 1 V power supply and the 50 μA input current.The current copy error is near zero at the input current of 27 μA.It consumes only 76 μW and introduces a very low output offset current of 50 pA.     

A low-voltage low-power instrumentation amplifier based on supply current sensing technique

In this paper a new low-voltage low-power instrumentation amplifier (IA) is presented. The proposed IA is based on supply current sensing technique where Op-Amps in traditional IA based on this technique are replaced with voltage buffers (VBs). This modification results in a very simplified circuit, robust performance against mismatches and high frequency performance. To reduce the required supply voltage, a low-voltage resistor-based current mirror is used to transfer the input current to the load. The input and output signals are of voltage kind and the proposed IA shows ideal infinite input impedance and a very low output one. PSPICE simulation results, using 0.18 μm TSMC CMOS technology and supply voltage of ±0.9 V, show a 71 dB CMRR and a 85 MHz constant −3 dB bandwidth for differential-mode gain (ranging from 0 dB to 18 dB). The output impedance of the proposed circuit is 1.7 Ω and its power consumption is 770 µW. The method introduced in this paper can also be applied to traditional circuits based on Op-Amp supply current sensing technique.     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².