A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don’t-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS’89 and ITC’99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

部分饱和SAR原始数据压缩

分块自适应量化(BAQ)算法在实际应用中碰到的问题是SAR原始数据含有较多饱和成分的量化。文中分析了BAQ对这类数据产生较大误差的原因。根据数据的特点,提出了一种对传统BAQ进行改良的压缩算法部分饱和BAQ(FSBAQ).实验表明,这种方法在不改变压缩比的情况下,对存在一定饱和的数据都能提高4.5dB以上的量化信噪比.文中给出了一条选择量化形式的曲线。并给出用传统BAQ算法及该文给出的算法对一块SAR原始数据进行量化和结果对比。     

Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells

While integrated circuits of ever increasing size and complexity necessitate larger test sets for ensuring high test quality, the consequent test time and data volume reflect into elevated test costs. Test data compression solutions have been proposed to address this problem by storing and delivering stimuli in a compressed format. The effectiveness of these techniques, however, strongly relies on the distribution of the specified bits of test vectors. In this paper, we propose a scan cell partitioning technique so as to ensure that specified bits are uniformly distributed across the scan slices, especially for the test vectors with higher density of specified bits. The proposed scan cell partitioning process is driven by an integer linear programming (ILP) formulation, wherein it is also possible to account for the layout and routing constraints. While the proposed technique can be applied to increase the effectiveness of any combinational decompression architecture, in this paper, we present its application in conjunction with a fan-out based decompression architecture. The experimental results also confirm the compression enhancement of the proposed methodology.

自适应量化编码的研究

本文详细地讨论了信源编码的原理,介绍了最优量化的方法以及自适应量化编码的原理。本文还给出一个自适应量化编码的实例。     

Test data compression using alternating variable run-length code

This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.     

软件测试用例集缩减的一个算法

一个测试用例集可能含有冗余的测试用例。在回归测试中为了减少维护测试用例集和执行测试用例的成本,可以采用测试用例集缩减的技术。文章提出了一个测试用例集缩减的新算法,并给出了应用实例。     

一种基于测试集分组的广义交替码

测试数据编码压缩是一类重要、经典的测试源划分（TRP）方法。本文提出了一种广义交替码,将FDR码、交替码都看作它的特例;又扩展了两步压缩方法,将原测试集划分成多组,每组采用不同的比值进行交替编码,综合了交替码与两步编码各自的优势,弥补了FDR码,交替码对某些电路测试集压缩的缺陷,得到了较好的压缩率。实验结果表明,与同类型的编码压缩方法相比,该方案具有更高的测试数据压缩率和较好的综合测试性能。     

边缘计算环境下的数据传输与处理技术研究

随着物联网设备的快速增加,边缘计算的必要性逐渐增长。在这些系统中,数据传输与处理技术决定了整个网络的效率和效能。文中重点分析了几种优化的传输和处理技术,包括自适应采样和压缩技术,并探讨了它们在边缘计算环境下的应用潜力。     

一种用于测试数据压缩的自适应EFDR编码方法

该文提出一种用于测试数据压缩的自适应EFDR(Extended Frequency-Directed Run-length)编码方法。该方法以EFDR编码为基础,增加了一个用于表示后缀与前缀编码长度差值的参数N,对测试集中的每个测试向量,根据其游程分布情况,选择最合适的N值进行编码,提高了编码效率。在解码方面,编码后的码字经过简单的数学运算即可恢复得到原测试数据的游程长度,且不同N值下的编码码字均可使用相同的解码电路来解码,因此解码电路具有较小的硬件开销。对ISCAS-89部分标准电路的实验结果表明,该方法的平均压缩率达到69.87%,较原EFDR编码方法提高了4.07%。     

Enhancement of test data compression with multistage encoding

In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.     

一种基于变长数据块相关性统计的 测试数据压缩和解压方法

为了解决系统芯片(SoC)测试过程中自动测试设备(ATE)在存储空间以及带宽等方面所面临的问题,本文提出了一种新的基于变长数据块相关性统计的测试数据压缩和解压方法.以测试向量为单位,先用算法确定一个具有最好相关性的数据块作为该向量的参考数据块,再利用它与该向量中数据块的相关性进行压缩.且每个向量的参考数据块长度相互独立.其解压结构只需要一个有限状态机(FSM)、一个5位暂存器和一个与参考数据块等长的循环扫描移位寄存器(CSR)即可,硬件开销小,对ISCAS-89标准电路Mintest集的压缩结果表明,本文提出方案较同类编码方法有更高的压缩效率.     

一种有效的合成孔径雷达原始数据高倍数压缩算法

在分析分块自适应量化(BAQ)压缩数据的分布特性、量化信噪比、动态范围及其对矢量量化数据压缩性能和运算量影响的基础上,对分块自适应矢量量化(BAVQ)压缩算法进行了改进,提出了采用高比特数BAQ压缩的方案.利用改进的BAVQ算法压缩高分辨率SAR原始数据的结果表明,在相同压缩比的条件下,该文提出的改进算法可获得更大的量化信噪比.解压缩数据生成的图像可以清晰地保留图像中的细节信息.     

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.     

采用字典词条衍生模式的测试数据压缩

为了降低数字集成电路测试成本,压缩预先计算的测试集是一种有效的解决途径。该文根据索引位数远少于字典词条,以及测试数据中存在大量无关位,提出一种采用词条衍生和二级编码的字典压缩方案。该方案引入循环移位操作,确保无关位按序任意移动而不丢失,从而扩大词条衍生性能,减少非词条向量个数。另外,采用规则的两级编码可以减少码字数量和解压电路的复杂度。实验结果表明该文所提方案能够进一步提高测试数据压缩率,减少测试时间。     

自适应字典压缩算法中的误码传播分析

在分析LZ77算法编译码原理的基础上,讨论了输入误码对译码字典和解压数据的影响,研究了误码传播问题。指出这些工作为消除误码传播、保证数据完整性具有重要意义。