Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents I_on more than double, while the off-state currents I_off remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher I_on increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design.     

Improving power analysis attack resistance using intrinsic noise in 3D ICs

Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks on the hardware implementation of cryptographic algorithms. However, neither physical experiments nor quantitative analysis is available in existing works to study the impact of power distribution network (PDN) on the SCA attacks. Through quantitative analyses and experiments with realistic 3D models, this work demonstrates the impact of noise in PDN on the 3D chip's resilience against correlation power analysis (CPA) attack, which is one of SCA attacks. The characteristic of PDN noise is extracted from our experiments. To expand the natural defense originated from the 3D integration, this work proposes to exploit the PDN noise inherently existing in 3D chips to thwart CPA attacks. Instead of introducing external noise or flattening the power profile, the proposed method utilizes the spatially and temporally varied supply voltages from other 3D planes to blur the power correlation of the crypto unit. Both theoretical analysis and experimental validation prove that the proposed method can effectively enhance the resilience of a crypto unit embedded in the 3D chip against CPA attacks. Simulation results show the proposed method improves the average guessing entropy by 9× over the baseline. Emulation on an FPGA platform demonstrates that the proposed method successfully slows down the key retrieval speed of CPA attack, with significantly less power overhead than representable power equalization techniques. Test vector leakage assessment (TVLA) shows that the proposed method improves the confidence to accept null hypothesis 201× over the baseline.     

Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback

This paper presents a comparative study among different biasing circuits of inductorless low-area Low Noise Amplifier (LNAs) with feedback. This study intends to determine the most suitable biasing circuit to achieve the best LNA performance for wideband applications. The main performance metrics are analyzed and a comparison is carried out based on electrical simulations. To this purpose, two different CMOS technology processes are considered: 130 nm and 90 nm. In both cases, the supply voltage is 1.2 V. The best LNA designed in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (A_v) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology designed in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are input-impedance matched and have a noise figure below 2.4 dB measured at 2.4 GHz. As a case study, the layout of the best-performance LNA circuit has been implemented in a 130 nm technology, achieving an area of 0.012 mm², which is near the size of a pad or an inductor. It is demonstrated that the bandwidth of this circuit can be notably increased by simply adding a small inductance in the feedback path.¹     

High performance parallel turbo decoder with configurable interleaving network for LTE application

In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving. This 2ⁿ-input network can be configured to support any 2ⁱ-input $(0\le i\le n)$ network. Furthermore, it can flexibly support arbitrary contention-free interleavers by cascading an additional specially designed network. In addition, an optimized decoding schedule scheme is presented to reduce the performance loss caused by high parallelism. Memory architecture and address mapping method are optimized to avoid memory access contention of small blocks. Moreover, a dual-mode add–compare–select (ACS) unit implementing both radix-2 and radix-4 recursion is proposed to support the block sizes that are not divided by 16. Implemented in 130 nm CMOS technology, the design achieves 384.3 Mbps peak throughput at clock rate of 290 MHz with 5.5 iterations. Consuming 4.02 mm² core area and 716 mW power, the decoder has a 1.81 bits/cycle/iteration/mm² architecture efficiency and a 0.34 nJ/bit/iteration energy efficiency, which is competitive with other recent works.     

A synchronous latency-insensitive RISC for better than worst-case design

Variability of process parameters in nanometer CMOS circuits makes standard worst-case design methodology waste much of the advantages of scaling. A common-case design, though, is a perilous alternative, as it gives up much of the design yield. Better than worst-case (BTWC) design methodology reconciles performance and yield. In this paper we present a BTWC RISC processor that tolerates worst-case extra delays of critical paths without significant impact on the overall performance. We obtain this result by coupling latency-insensitive design and variable-latency (VL) units. A software built-in self-test checks VL units individually to determine whether to activate them or not. Compared to a worst-case approach, the RISC clock frequency increases by 23% in a 45 nm CMOS technology. The impact of VL on instructions per cycle is circumscribed to the worst process case only and very limited, as we show through a set of benchmarks.     

Ultra-low-voltage boosted driver for self-powered systems

This paper deals with the ultra low-voltage design and application of an inverter-based driver. In order to ensure a reliable value of the overdrive voltage for transistors, the topology based on a boosting technique was used. The driver was designed in 130 nm CMOS technology and verified by simulations including technology corners and measurement of prototyped chips. The whole boosted driver achieves energy consumption of 92.12 μW for the load capacitor of 100 pF. Due to the low-power consumption and promising measured propagation delay, the designed driver was successfully implemented in a self-powered dynamic threshold charge pump. To ensure the reliable start-up, the minimum precharging voltage of the output capacitor has been investigated. The start–up conditions and achieved parameters were verified by measurement and compared to other related works. The optimum point for reliable start of the charge pump has been observed for the clock frequency of about 160 kHz, where the minimum start-up voltage of 126 mV is needed. In such a case, the start-up time is 1.05 ms and the output voltage of 379 mV will be reached.     

Ultra-low power m-sequence code generator for body sensor node applications

In this paper, a design of low power m-sequence code generator is proposed. The efficiency of producing the code sequence within the region of sub-threshold voltage is investigated using 90 nm technology and verified using the auto-correlation and eye diagram characterizations. A further method of power saving in addition to voltage reduction is carried out by scaling the technology node from 90 to 65 nm. A comparison of power consumption and maximum attainable frequency between both technologies is performed. The ratio of power saving while using 65 nm technology is ranging from 45% to 55% for the three different code lengths investigated.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection

A popular countermeasure against IP piracy is to obfuscate the Finite State Machine (FSM) which is assumed to be the heart of a digital system. Most of the existing FSM obfuscation strategies rely on additionally introduced set of obfuscation mode state-transitions to protect the original state-transitions of the FSM. Although these methods assume that it is difficult to extract the FSM behavior from the flattened gate-level netlist, some recent reverse engineering attacks could successfully break the defense of these schemes. The capability of differentiating obfuscation mode state-transitions from normal mode state-transitions makes these attacks powerful. As a countermeasure against these attacks, we propose a new strategy that offers a key-based obfuscation to each state-transition of the FSM. We use a special class of non-group additive cellular automata (CA), called D1 1 CA, and it's counterpart D11CA_dual to obfuscate each state-transition of the FSM. Each state-transition has its own customized key, which must be configured correctly in order to get correct state-transition behavior from the synthesized FSM. A second layer of protection to the state-transition logic enhances the security of the proposed scheme. An in-depth security analysis of the proposed easily testable key-controlled FSM synthesis scheme demonstrates its ability to thwart the majority of the state-of-the-art attacks, such as FSM reverse engineering, SAT, and circuit unrolling attacks. Thus, the proposed scheme can be used for IP protection of the digital designs. Experimentations on various IWLS′93 benchmark FSM designs show that the average area, power, and delay overheads our proposed multi-bit key-based obfuscated FSM design are 56.43%, 6.87%, and 23.41% while considering the FSMs as standalone circuits. However, experimentation on the Amber23 processor core shows these overheads drastically reduce (reported area, power, and delay overheads values are 0.0025%, 0.44%, and 0%, respectively) while compared with respect to the entire design.     

Impact of technology scaling on the tuning range and phase noise of mm-wave CMOS LC-VCOs

The impact of CMOS technology scaling, on the tuning range and phase noise performance of mm-wave LC voltage controlled oscillators (LC-VCOs) is presented. As a preliminary step, the fundamental LC-VCO elements (i) tank inductor, (ii) fixed and variable capacitor elements, and (iii) cross-coupled transistor pair are analytically modeled across the frequency range 10–50 GHz. These models are then exploited to analyze the tuning range and phase noise revealing the ultimate performance bounds for simultaneously achieving low phase noise and wide tuning range in mm-wave CMOS LC-VCOs across the CMOS technology scaling (from 130 nm down to 45 nm) are explored. The analysis demonstrates the improvement of the maximum achievable tuning range, phase noise, and figures-of-merit (FoM and FoM_T) with the technology down scaling. Finally, the performance trend of the mm-wave CMOS LC-VCOs implemented using both thin and thick gate cross-coupled pair is compared. The analysis indicates that thick gate cross-coupled pair VCOs achieve better phase noise at the expense of power consumption and maximum tuning range.     

A 45° dual dipole decomposition scheme to improve image fidelity

Dipole exposure techniques are currently being explored as alternatives to the low k1 problem that hinders the manufacture of sub 100 nm logic technology. Recently, there has been a great deal of interest in using a combination of vertical and horizontal dipole exposures capable of producing manufacturing-robust image results for Manhattan features. In this technique, a design is split into two complementary masks that have enhanced contrast at a given dipole imaging condition. The dipole is a strong case of off-axis illumination, and significant resolution enhancement can be achieved, but only for one pattern direction. Complementary dipole exposures are required when dense pitches in horizontal and vertical direction are present. Dipole decomposition approaches that separate vertical and horizontal features in a layout are based on the fact that horizontal features form an improved aerial image with a vertical dipole illumination, and vertical features show the same aerial image improvement with a horizontal dipole illumination. This technique, though conceptually simple, requires a computer algorithm to decompose a design layout into two patterns consisting of features oriented mainly in the horizontal and vertical directions. Some layout features, landing pads or angled lines for example, cannot easily be assigned to a particular mask based on this simple orientation logic. In this work a new approach has been presented in which 45° decomposition of the pattern is used to improve image contrast, pattern fidelity and focus behavior. The results will be analyzed in terms of contrast, pattern fidelity and focus dependence in order to determine the feasibility of printing manhattan and angled features using a dual dipole approach for sub 100 nm processes.     

Kernel-based template attacks of cryptographic circuits using static power

Side-channel attacks using static power have been shown to be successful against cryptographic circuits in different environments. This class of attacks exploits the power leakage when the circuit is in a static state, during which the power leakage is expected to be a fixed value. Due to the low signal-to-noise ratio of static power, usually more traces are needed for a static power attack to reach the same success rate as a dynamic power attack. The probabilistic distribution pattern of static power varies significantly in different devices, which further poses challenges to the accurate modeling of static power. In this paper we propose non-parametric template attacks which use a kernel methodology to improve the accuracy of modeling static power consumption. The proposed template attacks are tested using transistor-level simulations of circuits designed with a 45-nm standard cell library. Our test results show that our approach improves the success rate of template attacks using static power in cases where the distribution of static power consumption cannot be accurately modeled by Gaussian models.     

Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO₂-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node.     

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer

This paper presents a new design of a grounded active inductor (AI) with an improved topology based on Manetakis regulated cascode active inductor comprising of three control voltages for tunability. An additional pMOST was introduced in the design as a drain load at the output of nMOST source follower. The aim of this work is to design a CMOS AI at Ku band using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool. Firstly, a reasonable AI operating at Ku band was manually designed using a 130 nm technology. This circuit and its design variables were fed to AIDA-C as an element of the initial population. Then the sizing of the proposed AI MOSTs was optimized. AIDA-C circuit sizing tool is able to achieve not only one but a set of solutions for the AI exhibiting high quality factor at a predefined Ku band operating frequency. This set of alternative Pareto optimal solutions enables the designer to choose the most suitable circuit sizing for a given application. AI’s main performance parameters in terms of s parameters (s₁₁), quality factor (Q), inductance value (L), linearity, noise figure, power consumption and tunability based on control and biasing voltages are presented. Layout of the optimized AI is also presented. This AI was used to design active filters. Their selectivity, insertion losses and noise analysis is presented and discussed.     

An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications

In this paper, an area efficient and high throughput multi-rate quasi-cyclic low-density parity-check (QC-LDPC) decoder for IEEE 802.11n applications is proposed. An overlapped message passing scheme and the non-uniform quantization scheme are incorporated to reduce the overall area and power of the proposed QC-LDPC decoder. In order to enhance the decoding throughput and reduce the size of memories storing soft messages, an improved early termination (ET) scheme and base matrix reordering technique is employed. These techniques significantly reduce the total number of decoding iterations and memory accessing conflicts without mitigating the decoding performance. Equipped with these techniques an area efficient and high throughput multi-rate QC-LDPC decoder is designed, simulated and implemented with Xilinx Virtex6 (XC6VLX760-2FF1760) for an irregular LDPC code of length 1944 and code rates (1/2–5/6) specified in IEEE 802.11n standard. With a maximum clock frequency of 574.136–587.458 MHz the proposed QC-LDPC decoder can achieve throughput in the range of 1.27–2.17 Gb/s for 10 decoding iterations. Furthermore, by using Cadence RTL compiler with UMC 130 nm VLSI technology, the core area of the proposed QC-LDPC decoder is found to be 1.42 mm² with a power dissipation in the range of 101.25–140.42 mW at 1.2 V supply voltage.     

Efficient programmable power‐of‐two scaler for the three‐moduli set {2n+p, 2n − 1, 2n+1 − 1}

Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)–based DSPs, scaling represents a performance bottleneck based on the complexity of inter‐modulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well‐known moduli sets {2ⁿ ? 1, 2ⁿ, 2ⁿ + 1} and {2ⁿ, 2ⁿ ? 1, 2ⁿ⁺¹ ? 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic‐friendly moduli set {2^n+p, 2ⁿ ? 1, 2ⁿ⁺¹ ? 1}. The proposed algorithm yields high speed and energy‐efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed‐radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler.     

Design,simulation, and implementation of an integrated,hybrid photocurrent-to-digital converter in CMOS technology

This article presents a design, modeling, simulation, and measurements of a hybrid photocurrent-to-digital converter integrated together with photo-diodes in a 130 nm CMOS process, without any additional process steps. Photo-currents of integrated photo-diodes with different responsivities to different wavelength of the light and light intensity are converted into 22-bits digital results in 2 ms. The results can then be converted into CIE XYZ or RGB color luminosity space using dedicated DSP algorithm. A high resolution, hybrid, ADC converts light induced photo-currents into 22-bit digital results, canceling the dark current of the photodiodes and 1/f noise and offset voltage of the input stage of the modulator. The whole converter consumes on average less than current at supply voltage at 10 conversions per second. It occupies approx. 0.8 mm² of silicon area, including the three photodiodes, a multiplexer, and the ΣΔ modulator.     

Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization

Integration of Cu with low k dielectrics provided solution to reduce both resistance-capacitance time delay and parasitic capacitance of BEOL interconnections for 130 nm and beyond technology node. The motivation of this work is to study and improve electrical and reliability performance of two-level Cu/CVD low k SiOCH metallization from the results of diffusion barrier deposition schemes. Barrier deposition schemes are (a) high-density-plasma 250 Å Ta; (b) surface treatment of forming gas followed by high-density-plasma 250 Å Ta and (c) bi-layer of 100 Å Ta(N)/150 Å Ta. In this work, we demonstrated the superior and competency of high-density-plasma Ta deposition for Cu/CVD low k metallization and achieved excellent electrical and reliability results. Wafers fabricated with high-density-plasma Ta barrier scheme resulted in the best electrical yields, >90% for testing vehicles of dense via chains (via size=200 nm) and interspersed comb structures (width/space=200 nm/200 nm). Dielectric breakdown strength of the interspersed comb structures obtained at electric field of 0.3 MV/cm was ∼4 MV/cm.     

New types of cryptanalytic attacks using related keys

In this paper we study the influence of key-scheduling algorithms on the strength of blockciphers. We show that the key-scheduling algorithms of many blockciphers inherit obvious relationships between keys, and use these key relations to attack the blockciphers. Two new types of attacks are described: New chosen plaintext reductions of the complexity of exhaustive search attacks (and the faster variants based on complementation properties), and new low-complexity chosen key attacks. These attacks are independent of the number of rounds of the cryptosystems and of the details of the F-function and may have very small complexities. These attacks show that the key-scheduling algorithm should be carefully designed and that its structure should not be too simple. These attacks are applicable to both variants of LOKI and to Lucifer. DES is not vulnerable to the related keys attacks since the shift pattern in the key-scheduling algorithm is not the same in all the rounds.This research was supported by the fund for the promotion of research at the Technion.     

Low-Power Symmetrical Rectifier for Passive UHF RFID Transponder

Rectifier design is one of the challenging issues in passive radio-frequency identification (RFID) systems. Differential structures are good candidates as rectifiers to their high conversion efficiencies. In this paper, a novel structure is proposed to produce symmetrical power-supply utilizing differential circuit configuration simulated in 130nm CMOS technology. The proposed rectifier can provide 1.34 V DC power with 382% voltage conversion efficiency, thus demonstrated its higher performance over existing designs.