An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays

As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Correction Code (ECC) is a suitable solution. However, the more complex an ECC, the more delay, area usage and energy consumption. An ECC with an appropriate balance between error coverage and computational cost is essential for applications where fault tolerance is heavily needed, and the energy resources are scarce. This paper describes the conception, implementation, and evaluation of Column-Line-Code (CLC), a novel algorithm for the detection and correction of MCU in memory devices, which combines extended Hamming code and parity bits. Besides, this paper evaluates the variation of the 2D CLC schemes and proposes an additional operation to correct more MCU patterns called extended mode. We compared the implementation cost, reliability level, detection/correction rate and the mean time to failure among the CLC versions and other correction codes, proving the CLCs have high MCU correction efficacy with reduced area, power and delay costs.     

一种ECC校验算法的设计与实现

电可擦除可编程存储器(EEPROM)由于工艺结构的局限性而导致数据在存储过程中存在小概率的位反转问题。为解决该现象,设计了基于汉明码的纠错码(ECC)校验系统。结合EEPROM的结构特点和数据存储模式,该系统包含ECC校验码计算模块和数据检错纠错模块,每32 bit数据生成6 bit ECC校验码,具有1 bit/32 bit的纠错力。采用硬件描述语言Verilog HDL设计并实现了该ECC验证系统,并将其应用于基于串行外设接口(SPI)的EEPROM。仿真结果表明ECC验证系统可以保证数据的正确率,提高存储系统的可靠性。     

Efficient error detection in Double Error Correction BCH codes for memory applications

To prevent soft errors from causing data corruption, memories are commonly protected with Error Correction Codes (ECCs). To minimize the impact of the ECC on memory complexity simple codes are commonly used. For example, Single Error Correction (SEC) codes, like Hamming codes are widely used. Power consumption can be reduced by first checking if the word has errors and then perform the rest of the decoding only when there are errors. This greatly reduces the average power consumption as most words will have no errors. In this paper an efficient error detection scheme for Double Error Correction (DEC) Bose–Chaudhuri–Hocquenghem (BCH) codes is presented. The scheme reduces the dynamic power consumption so that it is the same that for error detection in a SEC Hamming code.     

Reliability of Hamming code transmission versus error probability on message bits

The paper presents an algorithm for the determination of the reliability of Hamming Code transmission against the error probability on message bits incurred during transmission. It establishes that Hamming Code is effective as long as the error probability of transmission line is less than 3%. The accuracy of Hamming Code drops to 90% when the error probability of the line is 8%. The algorithm is useful in adaptive communication circuits and is suitable for VLSI implementation.     

ELIMINATING SPEED PENALTIES IN ECC PROTECTED MEMORY DESIGNS USING “BIT BYPASSING” TECHNIQUES

In deep sub-micron ICs,growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems,such as soft errors induced by radiation.Error Correction Code （ECC） along with scrubbing is an efficient method for protecting memories against these errors.However,the latency of coding circuits brings speed penalties in high performance applications.This paper proposed a ＂bit bypassing＂ ECC protected memory by buffering the encoded data and adding an identifying address for the input data.The proposed memory design has been fabricated on a 130 nm CMOS process.According to the measurement,the proposed scheme only gives the minimum delay overhead of 22.6％,compared with other corresponding memories.Furthermore,heavy ion testing demonstrated the single event effects performance of the proposed memory achieves error rate reductions by 42.9 to 63.3 times.     

基于汉明纠错编码的AES硬件容错设计与实现

提出一种AES硬件容错设计可避免攻击者利用在AES设计环节中插入故障位实现攻击.在原有AES硬件设计中加入汉明码纠错电路,能自动纠正同一字节内的所有单比特故障,硬件仿真实验证明,故障发现率接近100%.针对不同AES设计结构和测试点配置对纠错电路的资源及速度进行了分析,实验结果表明我们提出的硬件容错设计有很强的可行性.     

Instruction-Vulnerability-Factor-Based Reliability Analysis Model for Program Memory

Bit faults induced by single-event upsets in instruction may not cause a system to experience an error. The instruction vulnerability factor (IVF) is first defined to quantify the effect of non-effective upsets on program reliability in this paper; and the mean time to failure (MTTF) model of program memory is then derived based on IVF. Further analysis of MTTF model concludes that the MTTF of program memory using error correcting code (ECC) and scrubbing is not always better than unhardened program memory. The constraints that should be met upon utilizing ECC and scrubbing in program memory are presented for the first time, to the best of authors’ knowledge. Additionally, the proposed models and conclusions are validated by Monte Carlo simulations in MATLAB. These results show that the proposed models have a good accuracy and their margin of error is less than 3 % compared with MATLAB simulation results. It should be highlighted that our conclusions may be used to contribute to selecting the optimal fault-tolerant technique to harden the program memory.     

Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System

With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.     

一种ECC加固SRAM空间可靠性评估算法

在SRAM抗辐射加固设计中,纠错编码(Error Correcting Code,ECC)是一种解决空间环境中SRAM单粒子翻转效应的有效方法。但目前国内外对于基于ECC加固的SRAM可靠性评估体系的研究并不完全成熟,还没有一个统一的标准。基于空间环境下SRAM所产生软错误的错误分布图样特性和错误重叠特性,对已有的基于ECC加固的SRAM空间可靠性评估方案进行修正,得到了一种更加精确的评估模型。     

A 250-MHz skewed-clock pipelined data buffer

A synchronous dual-port memory employing a three-transistor (3T) dynamic cell has been designed for use as a high throughput embedded data buffer in digital switching and signal processing applications. Skewed-clock pipelining is used to achieve operation at frequencies as high as 250 MHz with a low register element count. The 3T cell provides separate read and write access ports while occupying less than half the area of a conventional dual-port SRAM cell. On-chip Hamming error correction coding (ECC) is used to enhance the fault tolerance of the memory, A 25-kb experimental prototype has been integrated in a 0.8-μm CMOS technology; it occupies a die area of 3800 μm×1600 μm and dissipates 420 mW while operating at 250 MHz     

一种基于编码的存储器加固设计

在太空辐射环境中存在各种宇宙射线和一些高能粒子,其中单粒子翻转（SEU）效应是引起存储器软错误的重要因素,降低了数据传输的可靠性,因此成为当前集成电路抗辐射加固设计的研究重点之一。标准的纠错编码（ECC）设计冗余度将占用超过50%的存储量,该设计基于缩短汉明码的原理实现了对32位存储器采用7位冗余码进行纠错编码的SEC-DED加固设计,在资源上得到了优化;同时从概率的角度分析了可靠性的理论基础,通过编码可靠性可以提高3到6个数量级。     

A compact on-chip ECC for low cost flash memories

A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10^-4 to 10^-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA     

A Software Technique for Diagnosing and Correcting Memory Errors

A software diagnostic that eliminates 2-bit and some 3-bit errors is described. The diagnostic procedure tests memory for errors that cannot be corrected by ECC (error correcting code): single error correct, double error detect. When an uncorrectable error is found, the diagnostic attempts to reduce it to a I-bit error. This is done either by reconfiguring the memory to distribute failing bits across different ECC words or by replacing the failing chip with a spare. The result is that memory cards that previously had to be replaced can now continue to function. Thus, the life of memory cards can be prolonged. The diagnostic can also perform preventive maintenance when run in an alternate mode. In this mode, all combinations of the memory are tested to determine if there is reserve. Reserve is defined as: 1) The capability of reconfiguring the card to obtain another functional state of memory (in addition to the current operational state), or 2) The availability of functional spare chips that have not been used. Preventive maintenance is by replacing cards that have no reserve. Then, memory operation can continue error free.     

基于FPGA和NAND Flash的存储器ECC设计与实现

针对以NAND Flash为存储介质的高速大容量固态存储器,在存储功能实现的过程中可能出现的错“位”现象,在存储器的核心控制芯片,即Xilinx公司Virtex-4系列FPGA XC4VLX80中,设计和实现了用于对存储数据进行纠错的ECC算法模块。在数据存入和读出过程中,分别对其进行ECC编码,通过对两次生成的校验码比较,对发生错误的数据位进行定位和纠正,纠错能力为1 bit/4 kB。ECC算法具有纠错能力强、占用资源少、运行速度快等优点。该设计已应用于某星载存储系统中,为存储系统的可靠性提供了保证。     

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word×16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8-μm CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 μm² with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC     

一种简单分组码编、译码器的单片机实现方案

本论文给出了一种简单分组码-(7,4)汉明码编、译码器的单片机实现方案.在硬件实现上验证了(7,4)汉明码的纠一位随机错误能力和交织度为2时的纠两位突发错误的能力.     

Peak‐to‐Average Power Ratio Reduction Using N‐tuple Selective Mapping Method for MC‐CDMA

The multi‐carrier transmission signal in Multi‐Carrier Code Division Multiple Access (MC‐CDMA) has a high peak‐to‐average power ratio (PAPR), which results in nonlinear distortion and deteriorative system performance. An n‐tuple selective mapping method is proposed to reduce the PAPR, in this paper. This method generates 2ⁿ sequences of an original data sequence by adding n‐tuple of n PAPR control bits to it followed by an interleaver and error‐control code (ECC) to reduce its PAPR. The convolutional, Golay, and Hamming codes are used as ECCs in the proposed scheme. The proposed method uses different numbers of the n PAPR control bits to accomplish a noteworthy PAPR reduction and also avoids the need for a side‐information transmission. The simulation results authenticate the effectiveness of the proposed method.     

Memory Reliability Improvement Based on Maximized Error-Correcting Codes

Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some widespread ECCs. A method is proposed for the selection of multi-bit errors that can be additionally corrected with a minimal impact on ECC decoder latency. These methods were applied to single-bit error correction (SEC) codes and double-bit error correction (DEC) codes. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are independent and identically distributed. It is shown that the application of the proposed methods to conventional DEC codes can improve the mean-time-to-failure (MTTF) of memories with up to 30 %. Maximized versions of the DEC codes are also proposed in which all adjacent triple-bit errors become correctable without affecting the maximum number of triple-bit errors that can be made correctable.     

Design and characterization of an error-correcting code for theSONET STS-1 tributary

The authors have designed and characterized a single-error-correcting (SEC), double-error-detecting (DED) code applicable to the STS-1 SONET format. They show that if two of the presently unallocated bytes in the path overhead field of STS-1 are assigned for error-correction coding (ECC), a {6208, 6195} shortened extended Hamming code can be implemented using as few as 660 gates plus a 1-kbyte RAM IC, achieving (O8.6×10^-3 P ₂²) BER reduction with 139 μs of signal delay. The authors explain how the existing BIP-8 error-monitoring byte of the STS-1 format could be integrated with the proposed ECC so that a net allocation of only one new STS-1 overhead byte is required for both error monitoring and error correction. The implementation method is such that all path, line, and section overhead functions in SONET can be performed at intermediate sites without requiring ECC decoding. The authors consider application alternatives and describe the forward-error-correction (FEC) circuit design and trial results. System issues are covered, including network delay, effects of error extension on BER, addition of double-error detection, performance monitoring, and options for intelligent network control and management of FEC functions. Codes related to their path-level design that are applicable to a number of other strategies for applying FEC in SONET are presented     

A transparent online memory test for simultaneous detection of functional faults and soft errors in memories

The Transparent Online Memory Test (TOMT) introduced here has been specifically developed for online testing of word-oriented memories with parity or Hamming protection. Careful interleaving of a word-oriented and a bit-oriented test facilitates a fault coverage and a test duration comparable to the widely used March C- algorithm. Unlike similar methods TOMT actively exercises all bit cells in memory within one test period. Hence it not only detects soft errors but also functional faults and reliably prevents fault accumulation. Different variants of the basic TOMT algorithm are investigated in terms of fault coverage and test time. A prototype implementation for SRAM is introduced which-integrated into a standard processor/memory interface-autonomously performs the transparent online memory test. The trade-offs in terms of hardware overhead and memory access delay caused by this system integration are explored.