A High-Order Temperature-Compensated Subthreshold Voltage Reference Using Channel Length Modulation Compensation Technique

The paper presents a novel high-order temperature-compensated subthreshold voltage reference that utilizes temperature characteristics of the gate-to-source voltage of subthreshold MOS transistor. The proposed high-order temperature-compensated voltage reference has been designed using two CMOS voltage references and a current subtraction circuit to achieve a low temperature coefficient over a wide temperature range. The proposed circuit offers an output reference voltage of 250.8 mV, line sensitivity of 0.0674%/V and temperature coefficient of 37.4 ppm/°C for the temperature range varying from???20 \(\mathrm{^\circ{\rm C} }\) to 140 °C at nominal conditions. The power supply rejection ratio is obtained as???46.02 dB at a frequency of 100 Hz and???41.91 dB at a frequency of 1 MHz. The proposed circuit shows an output noise of 1.86 \(\mathrm{\mu V}/\surd \mathrm{Hz}\) at 100 Hz and 259.72 \(\mathrm{nV}/\surd \mathrm{Hz}\) at 1 MHz. The proposed circuit has been designed in BSIM3V3 180 nm CMOS technology using Cadence tool. The corner analysis of the proposed circuit has also been performed to show its performance in extreme conditions. The proposed circuit occupies a small chip area of 51 \(\upmu\)m?×?75.3 \(\upmu\)m.

     

Design and realization of an ultra-low-power low-phase-noise CMOS LC-VCO

A fully integrated cross-coupled LC tank voltage-controlled oscillator(LC-VCO) using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μm CMOS technology of SMIC. The measured phase noise is-125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz,while the VCO core circuit draws only 640μW from a 0.4-V supply.The designed VCO can...     

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I-V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient of 2.5×10⁻⁴ μA/°C in the temperature range of −40 to 150 °C at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126 dB at dc frequency and remains −92 dB at the frequency higher 1 MHz. The proposed circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

A low power Gm-C filter with on-chip automatic tuning for a WLAN transceiver

A sixth-order Butterworth Gm-C low-pass filter(LPF)with a continuous tuning architecture has been implemented for a wireless LAN(WLAN)transceiver in 0.35 μm CMOS technology.An interior node scaling technique has been applied directly to the LPF to improve the dynamic range and the structure of the LPF has been optimized to reduce both the die size and the current consumption.Measurement results show that the filter has 77.5 dB dynamic range,16.3 ns group delay variation,better than 3% cutoff frequency accuracy,and 0 dBm passband IIP3.The whole LPF with the tuning circuit dissipates only 1.42 mA(5 MHz cutoff frequency)or 2.81 mA(10 MHz cutoff frequency)from 2.85 V supply voltage,and only occupies 0.175 mm2 die size.     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.     

A 12-mW 264-MHz high linearity sharp roll-off CMOS opamp-RC low-pass filter for MB-OFDM UWB systems

This paper presents a high linearity wideband sharp roll-off Opamp-RC low-pass filter (LPF) for Ultra wideband (UWB) applications. The proposed LPF is composed of three biquads’ transfer functions with different Q-factors in series. Sharp roll-off is attributed to the steep slope of the peaking of a biquad transfer function with a high Q-factor. The superposition of these biquads also helps extend the bandwidth of the overall LPF transfer function without the cost of extra power dissipation. The effects of biquad arrangements on noise and linearity performances are investigated. A simple operational amplifier (op-amp) is adopted to ensure high frequency characteristics and high linearity performance for the designed filter. The LPF is implemented in 0.13-μm IBM CMOS process from 1.5 V supply. The measured cutoff frequency is 264 MHz with the pass-band ripple of less than 1 dB. Digital frequency tuning is implemented with 40% of tuning range around the cutoff frequency. The amount of out-of-band rejection at 290 MHz and at twice cutoff frequency is 12 dB and about 50 dB, respectively. Good linearity with IIP3 of 23 dBm is obtained. The 6th-order LPF dissipates only 12 mW with the active chip size of 400 × 640 μm².     

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8  nW at 0.6 V supply. The active area is 0.019 mm².     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

This paper describes the design and realization of a sub 1-V low power class-AB bulk-driven tunable linear transconductor using a 0.18-μm CMOS technology. The proposed transconductor employs a class-AB bulk-driven differential input voltage follower and a passive resistor to achieve highly linear voltage-to-current conversion. Transconductance tuning is achieved by tuning the differential output current of the core transconductor with gain-adjustable current mirrors. With 10.4-μA current consumption from a 0.8-V single power supply voltage, simulation results show that the proposed transconductor achieves the total harmonic distortion (THD) of <?40 dB for a peak differential input voltage range of 800 mV at frequencies up to 10 kHz. The simulated input-referred noise voltage integrated over 10-kHz bandwidth is 100 μV, resulting to an input signal dynamic range of 75 dB for THD <?40 dB. A biquadratic G_m-C filter is designed to demonstrated the performance of the proposed transconductor. At the nominal 10-kHz cut-off frequency, the filter dissipates 34.4 μW from a 0.8-V supply voltage and it achieves an input signal dynamic range of 67.4 dB for the third-order intermodulation distortion of <?40 dB.     

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35μm SiGe BiCMOS technology. The filter's -3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has -0.5 dB passband gain, +/- 5% bandwidth accuracy, 30 nV/Hz1/2 input referred noise, -3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f0 = 20 MHz) from 5 V supply, and occupy 0.5 mm2.     

一种用于生物信号采集的CMOS全差分前置跨阻放大器设计

针对生物信号微弱、变化范围大等特点设计了一种用于检测微弱电流的全差分跨阻放大器(TIA)电路结构。不同于传统电路的单端输入,该结构采用高增益的全差分两级放大器实现小信号输入及轨到轨输出。基于CSMC 0.18μm CMOS工艺,采用1.8V电源电压对设计的电路进行了仿真,仿真结果表明:TIA输入电流动态范围为100nA^10μA,最大跨阻增益达到104.38dBΩ,-3dB带宽为4MHz,等效输入噪声电流为1.26pA/Hz。对电路进行跨阻动态特性仿真表明,在输入电流为100nA时,输出电压的动态摆幅达到3.24mV,功耗仅为250μW,总谐波失真(THD)为-49.93dB。所设计的高增益、低功耗、宽输入动态范围TIA适用于生物医疗中极微小生物信号的采集,可作为模块电路集成在便携设备中。     

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as f_T-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 2³¹–1 with a bit-error rate (BER) of 10⁻¹² at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mV_pp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.     

10Gb/s光接收机跨阻前置放大器芯片设计研究

采用0.18 μm BiCMOS工艺设计并实现了一种高增益、低噪声、宽带宽以及大输入动态范围的光接收机跨阻前置放大器.在寄生电容为250 fF的情况下,采用全集成的四级放大电路,合理实现了上述各项参数指标间的折中.测试结果表明:放大器单端跨阻增益为73 dB,-3 dB带宽为7.6 GHz,灵敏度低至-20.44 dBm,功耗为74 mW,最大差分输出电压为200 mV,最大输入饱和光电流峰-峰值为1 mA,等效输入噪声为17.1 pA/√Hz,芯片面积为800 μ.m×950μm.     

Low noise accelerometer microsystem with highly configurable capacitive interface

This paper presents a low noise accelerometer microsystem with a highly configurable capacitive interface circuit. A programmable capacitive readout circuit is designed to minimize the offset and gain error due to the parasitic capacitance mismatch and the process variations. The interface circuit is implemented in a 0.5 μm 2P3M CMOS technology with EEPROM. The interface circuit and MEMS sensing element are integrated in a single package, and consist the accelerometer microsystem. The supply voltage and supply current of the system are 5 V and 1.17 mA, respectively. The input range and gain are 2.5 V and 0.5 V/g, respectively. The max–min gain error and max–min offset error after calibration was measured to be 1.2% FSO and 3.3% FSO, respectively. The signal to noise ratio (SNR) and noise equivalent resolution (NER) are measured to be 93.1 dB and 110.6 μg/√Hz, respectively, when a 40 Hz, 5 g sinusoidal input acceleration is applied.     

Low power time-domain rail-to-rail comparator with a new delay element for ADC applications

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step.     

Low-power CMOS switched-capacitor lowpass filter using current conveyors

A new approach is proposed to the design of high-order switched-capacitor LPFs of megahertz cutoff frequency for communications channel selection. It essentially uses current conveyors instead of op amps to achieve low power consumption. A fifth-order Chebyshev LPF with a 1-MHz cutoff frequency is thus synthesized and fabricated in a 0.35-μm CMOS technology. The LPF consumes less than 10 mW from a 3-V power supply and exhibits a third harmonic distortion better than ?54 dB in response to a 1-V sinusoidal input at the cutoff frequency. The rms noise voltage is at most 1.9 mV in a 2-MHz bandwidth.     

Ultra-Wideband, Low-Power, Inductorless, 3.1�C4.8?GHz, CMOS VCO

A low-power, inductorless, UWB CMOS voltage controlled oscillator is designed in 0.18 μm CMOS technology targeting to a UWBFM transmitter application. The VCO is a Double-Cross-Coupled Multivibrator and generates output frequencies ranging from 1.55 GHz to 2.4 GHz. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range from 3.1 GHz to 4.8 GHz. The proportionality between the oscillation frequency and the bias current is avoided in this case for the entire achieved tuning range resulting in a low-power design. The selected architecture provides high suppression, over 45 dB, for the 1^st and 3^rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The proposed VCO draws 4 mA from a 1.8 V supply, it has a phase noise of −76.7 dBc/Hz at 1 MHz offset from the center frequency, while it exhibits a very high ratio of tuning range (43%) over power consumption equal to 7.76 dB.     

A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-$mu$ m CMOS

This paper presents a 100-kHz fifth-order Chebychev low-pass filter (LPF) using the proposed dynamic biasing (DB) technique which enables wide dynamic range under a low-supply voltage. The change of state variables in the internal nodes of the filter can be corrected by using a novel simplified scheme, avoiding the output transient owing to dynamic biasing. The filter, including an automatic frequency tuning system based on the voltage-controlled-filter (VCF) architecture and voltage reference circuit, is fabricated in a 0.18-mum standard CMOS technology with a 0.5-V threshold voltage and consumes 443 muW from a power supply of 0.6 V. The output noise and the in-band IIP₃ are 575 pA_rms and 219 muA, respectively. The filter achieves a dynamic range of 89 dB.