Wide‐band dual‐resonance capacitive cross‐coupled divide‐by‐5 injection‐locked frequency divider

A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias V_DD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm².     

Design methodology for common‐mode stability of OTA‐based gyrators

This paper presents a design methodology for common‐mode (CM) stability of operational transconductance amplifier (OTA)‐based gyrators. The topology of g_m ? C active inductors is briefly reviewed. Subsequently, a comprehensive mathematical analysis on the CM stability of OTA‐based gyrators is presented. Sufficient requirements for the gyrator's CM stability, which easily can be considered during the design process of common‐mode feedback (CMFB) amplifiers, are defined. Based on these stability requirements, a design methodology and a design procedure are proposed. Finally, in order to validate the proposed procedure, a resonator with 20 MHz resonance frequency and a quality factor of 20 is fabricated with UMC 180 nm complementary metal‐oxide‐semiconductor technology, and its CM stability is examined. Copyright © 2015 John Wiley & Sons, Ltd.     

Piezoresistive property of an aluminum‐doped zinc oxide thin film deposited via atomic‐layer deposition for microelectromechanical system/nanoelectromenchanical system applications

The piezoresistive property of an aluminum (Al)‐doped zinc oxide (AZO) thin film (thickness = 20 nm) is evaluated using a microfabricated silicon cantilever structure. The AZO thin film is deposited via atomic‐layer deposition with 5% Al doping. An AZO piezoresistor is patterned at the root of the cantilever. This cantilever device is fabricated using conventional microfabrication techniques such as lithography, lift‐off, ion milling, and dry/wet etching. The cantilever is deflected by pressing the tip of the cantilever by a needle mounted on a micromanipulator. The strain of the AZO pattern caused by the deflection is numerically calculated using a finite element method based on the dimensions and materials of the fabricated device. The output current of the AZO changes almost linearly with increase in the input voltage. The gauge factor of the AZO thin‐film piezoresistor is found to be 8.5.     

Mode‐matching analysis of a spit‐circular cavity resonator for measurement of the dielectric constant for film on a substrate

In this paper, we apply the mode‐matching technique (eigenmode expansion) to formulate an analytical model for a split cylindrical cavity resonator with a thick ceramic film layer sandwiched between two‐layer alumina substrates. We then compute the resonant frequencies with the TE₀₁₁ mode with an eigenvalue problem approach using the model formula. The quality factor (Q ‐factor) of the resonator is also calculated by applying the perturbation method to the analytical model. The validity of the proposed analytical technique is confirmed by applying this method to the estimation of permittivity of thick films as an inverse problem. Ceramic films (2 µm thickness) were synthesized using a chemical solution method onto 200‐µm‐thick, 50‐mm‐diameter alumina substrates. The complex permittivity of the films was then determined using the TE₀₁₁ mode split cylindrical cavity resonator in the 10‐GHz band. The extent of the edge effect at a sample insertion space was evaluated by comparing the estimated results through TE wave analysis using the mode‐matching method when the transverse resonance technique and the perturbation method were applied to calculate the resonant frequency and the dielectric Q ‐factor. The results obtained indicate that a difference of 0.153% in the permittivity of the alumina substrate causes differences of 6.10 and 3.75% in the measured permittivity and loss tangent, respectively, of 2‐µm‐thick ceramic film with a permittivity of ∼50. Differences in permittivity and loss tangent were more pronounced with thinner films. It was also confirmed that the estimated results for permittivity and the loss tangent values of these ceramic films were affected by the estimated permittivity value of the alumina substrate. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Q‐factor evaluation,design and accurate EM performance of multilayer dielectric filters

In this contribution we present the design of an optical dielectric multilayered filter by using a transmission‐line prototype. Each resonator of the prototype is realized by means of a stack of dielectric layers by equating the Q‐factor of the stack with that of the corresponding resonator of the prototype. We then compare the analytical results with numerical ones obtained by the finite element method (FEM). We extend the theory to a structure formed by periodic multilayer resonators. Copyright © 2006 John Wiley & Sons, Ltd.     

Low‐resistive and transparent AZO films prepared by PLD in magnetic field

Al₂O₃‐doped ZnO (AZO) thin films have been deposited onto glass substrates using a split target consisting of AZO (1 wt%) and AZO (2 wt%) by pulsed laser deposition with an ArF excimer laser (λ = 193 nm, 15 mJ, 10 Hz, 0.75 J/cm²). By applying a magnetic field perpendicular to the plume, the lowest resistivity of 8.54 × 10^?5Ω·cm and an average transmittance exceeding 91% over the visible range were obtained at a target‐to‐substrate distance of 25 mm for approximately 279‐nm‐thick AZO film (1.8 wt%) grown at a substrate temperature of 230 °C in vacuum. From cross‐sectional TEM observations and the XRD spectrum, a reason why the low resistivity (54 × 10^?5Ω·cm) was reproducibly obtained was considered to be due to the fact that a disorder of crystal growth originating in the vicinity of the interface between the substrate and the film was suppressed by application of the magnetic field and the c‐axis orientation took preference, giving rise to the increase of mobility. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 151(2): 40–45, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20026     

Divide‐by‐2 LC injection‐locked frequency divider with wide locking range at low and high injection powers

A wide locking range nMOS divide‐by‐2 RLC injection‐locked frequency divider (ILFD) was designed and implemented in the TSMC 0.18‐µm BiCMOS process. The ILFD is based on a cross‐coupled oscillator with one direct injection MOSFET and a RLC resonator. The RLC resonator is used to extend the locking range so that dual‐band locking ranges can be merged in one locking range at both low and high injection powers. At the drain‐source bias of 0.9 V for switching transistors, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 7.24 GHz, from the incident frequency 2.65 to 9.89 GHz, the locking range percentage is 115.47%. The power consumption of ILFD core is 8.685 mW. The die area is 0.726 × 0.930 mm². Copyright © 2016 John Wiley & Sons, Ltd.     

Threshold voltage extraction techniques adaptable from sub‐micron CMOS to large‐area oxide TFT technologies

This paper proposed simple and accurate threshold voltage (V _TH ) extraction techniques, which can be directly adaptable to various semiconductor technologies ranging from deep sub‐micron complementary metal–oxide–semiconductor to large‐area thin‐film transistor devices. These techniques are developed using multiple circuits, namely, a dynamic source follower, an inverter with a diode‐connected load and a current mirror topology, which allow a direct determination of V _TH . As the proposed techniques are experimented with large‐area emerging technologies, which have a stable single type (n‐type) transistor, all the designs employed in this work are confined to only n‐type transistors for a fair comparison. The semiconductor technologies under consideration are standard complementary metal–oxide–semiconductor (65 and 130 nm) and oxide (indium–gallium–zinc–oxide and zinc–tin–oxide) thin‐film transistors. In order to validate the accuracy of the proposed techniques, extracted V _TH from these methods are compared against the value from linear transfer characteristics. The resulting relative error is within 5%, reinforcing proposed techniques suitability to different semiconductor technologies ranging from deep sub‐micron to large‐area transistors. Copyright © 2017 John Wiley & Sons, Ltd.     

State‐space equations of regular and strictly topologically degenerate linear lumped time‐invariant networks: the multiport method

A new complete approach to the multiport formulation of the state‐space equations of uniquely solvable regular or strictly topologically degenerate linear lumped time‐invariant networks is presented. It is based on a Gedankenexperiment during which the topological structure of the original network is manipulated in various ways. The final method requires one to calculate the describing matrices of three homogeneous multiports (i.e. a capacitive, an inductive and a resistive one), which are obtained from the network of interest in a very simple manner. As a by‐product, the equivalent partitioned network is also derived. As an example of application, the state‐space equations of a fourth‐order strictly topologically degenerate network are provided. Copyright © 2001 John Wiley & Sons. Ltd.     

Wide‐band divide‐by‐2 injection‐locked frequency divider using MOSFET mixers DC‐biased in subthreshold region

A novel wide locking range divide‐by‐2 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18‐µm 1P6M CMOS process. The divide‐by‐2 ILFD is based on a cross‐coupled voltage‐controlled oscillator (VCO) with an LC resonator and injection MOSFETs with source voltage coupled from ILFD output, and the injection MOSFET mixer is biased in subthreshold region. At the drain–source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 6.4 GHz; from the incident frequency 3.7 GHz to 10.1 GHz, the percentage is 92.75%. The core power consumption is 16.56 mW. The die area is 0.839 × 0.566 mm². Copyright © 2015 John Wiley & Sons, Ltd.     

Current‐mode dual‐output ICCII‐based tunable universal biquadratic filter with low‐input and high‐output impedances

A new tunable current‐mode (CM) biquadratic filter with three inputs and three outputs using three dual‐output inverting second‐generation current conveyors, three grounded resistors and two grounded capacitors is proposed. The proposed circuit exhibits low‐input impedance and high‐output impedance which is important for easy cascading in the CM operations. It can realize lowpass, bandpass, highpass, bandreject and allpass biquadratic filtering responses from the same topology. The circuit permits orthogonal controllability of the quality factor Q and resonance angular frequency ω_o, and no component matching conditions or inverting‐type input current signals are imposed. All the passive and active sensitivities are low. Hspice simulation results are based on using TSMC 0.18 µm 1P6M process complementary metal oxide semiconductor technology and supply voltages ±0.9 V to verify the theoretical analysis. Copyright © 2012 John Wiley & Sons, Ltd.     

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.     

Application of duality principle to synthesis of single‐stage power‐factor‐correction voltage regulators

The duality principle is applied to derive new single‐stage power‐factor‐correction (PFC) voltage regulators. This paper begins with an application of duality transformation to conventional discontinuous‐conduction‐mode buck, buck‐boost and boost converters. The resulting dual converters operate in the discontinuous capacitor voltage mode. These new converters provide the same PFC property, but in the dual manner. It is proved that in the practical case of the input being a voltage source, the mandatory insertion of inductance between the voltage input and the ‘dual PFC converter’ does not affect the power‐factor‐correcting property. A new single‐stage PFC regulator is derived by taking the dual of a well‐known circuit based on a cascade of conventional boost and buck converters. Analytical design expressions are derived, illustrating the relation between current stress and component values. Experiments are performed to confirm the operation of the circuit and its power‐factor‐correcting capability. Copyright © 2003 John Wiley & Sons, Ltd.     

Highly elongated,low‐aspect‐ratio tokamak produced by negative‐biased theta pinch

Ultra Low Aspect Ratio Tokamaks (ULART) are produced by using a negative‐biased theta‐pinch device. A slender conducting rod which serves as a toroidal field coil is newly installed along a geometrical center axis of the theta‐pinch coil. The ULART is quickly formed for about 10 μs by applying programmed current flows from three sets of fast banks and a slow bank to these coils and is sustained for about 100 μs. The plasma diagnosed from a magnetic probe array has a low aspect ratio A = 1.1 and a poloidal surface with a high elongation ratio κ = 10. The safety factor reaches about 30 near the separatrix edge when I_p = 280 kA flows in the plasma and I_tfc = 30 kA in the conducting rod. A preliminary result on global MHD characteristics of the ULART is also given. The plasma is unstable with respect to a vertical displacement and a toroidal n = 1 mode. The amplitudes of these modes depend on the values of I_tfc and κ. © 2001 Scripta Technica, Electr Eng Jpn, 134(4): 19–27, 2001     

A switch‐utilization‐improved switched‐inductor switched‐capacitor converter with adapting stage number

A novel closed‐loop switched‐inductor switched‐capacitor converter (SISCC) is proposed by using the pulse‐width‐modulation (PWM) compensation for the step‐up DC–DC conversion/regulation, and together by combining the adaptive‐stage‐number (ASN), control for the higher switch utilization and wider supply voltage range. The power part of SISCC is composed of two cascaded sub‐circuits, including (i) a serial‐parallel switched‐capacitor circuit with n_c pumping capacitors and (ii) a switched‐inductor booster with m_c resonant capacitors, so as to obtain the high step‐up gain of (n_c + 1) × m_c /(1 ? D) at most, where D is the duty cycle of PWM adopted to enhance output regulation as well as robustness to source/loading variation. Besides, the ASN control is presented with adapting the stage number n (n = 0, 1, 2, …, n_c) of pumping capacitors to obtain a flexible gain of (n + 1) × m_c /(1 ? D), and further in order to make the SISCC operating at a properly small duty cycle for improving switch utilization and/or supply voltage range. Some theoretical analysis and control design include formulation, steady‐state analysis, ASN‐based conversion ratio, efficiency, output ripple, stability, inductance and capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on an ASN‐based SISCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2015 John Wiley & Sons, Ltd.     

A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS

A low‐power low‐jitter voltage‐mode (VM) transmitter with two‐tap pre‐emphasis and impedance calibration for high‐speed serial links is presented. Based on a comprehensive analysis of the relationship between impedance, supply current, and pre‐emphasis of the output driver, an impedance control circuit (ICU) is presented to maintain the 50 Ω output impedance and suppress the reflection, a self‐biased regulator is proposed to regulate the power supply, and an edge driver is introduced to speed up the signal transition time. Therefore, the signal integrity (SI) of the transmitter is improved with low power consumption. The whole transmitter is implemented in 65‐nm CMOS technology. It provides an eye height greater than 688 mV at the far end with a root‐mean‐squared jitter of less than 6.99 ps at 5 Gbps. The transmitter consumes 15.2 mA and occupies only 370 μm × 230 μm. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A simulation study of high‐order CMOS hyperbolic‐sine filters

This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and f_o = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

Fifth‐order Π‐type load resonant converters analysis based‐on immittance property for constant output current applications

Passive resonant tanks (PRTs) with immittance property are suitable candidates to achieve constant output current in load resonant converters (LRCs). In this paper, fifth‐order Π‐type LC networks are investigated to accede this target. At the first step, fifth‐order Π‐type passive LC networks that can be applied as a PRT are specified based on source and sink natures. Also, their structural advantages are described in detail to give a suitable perspective for the topology selection. At the second step, immittance property is verified for the proposed topologies and immittance PRTs (IPRTs), with their immittance operation conditions, are derived. To confirm the effectiveness, a 150‐W LRC is implemented leveraging new Π‐type IPRTs. A deep investigation is devoted to analyze the current/voltage stress in the components of the designed LRC. Moreover, kVA/kW ratio is considered as a key parameter for the reactive component size minimization. The proposed constant current LRC presents high load regulation capability in addition to the minimum reactive power and zero‐voltage switching (ZVS) on the inverter MOSFETs under the various loads. A significant robustness against load variations, less sensitivity versus parameters variation, and relatively higher efficiency are the main superiorities of the fifth‐order IPRTs to the lower order counterparts.     

A gain/efficiency‐enhanced bidirectional switched‐capacitor DC‐DC converter

A closed‐loop gain/efficiency‐enhanced bidirectional switched‐capacitor converter (BSCC) is proposed by combining an adaptive‐conversion‐ratio (ACR) phase generator and pulse‐width‐modulation (PWM) controller for bidirectional step‐up/down DC‐DC conversion and regulation. For realizing gain‐enhanced, the power part consists of one m_c‐stage cell and one n_c‐stage cell in cascade between low‐voltage (LV) and high‐voltage (HV) sides to boost HV voltage into m_c × n_c times voltage of LV source at most, or convert LV voltage into 1/(m_c × n_c) times voltage of HV source at most. For realizing efficiency‐enhanced, the ACR idea with adapting stage number m, n is built in the phase generator to obtain a suitable step‐up/down gain: m × n or 1/(m × n) (m = 1, 2, …, m_c, n = 1, 2, …, n_c). Further, the output regulation and robustness to source/loading variation can be enhanced by PWM on the LV/HV sides. Some theoretical analysis and control design are included as: modeling, steady‐state analysis, conversion ratio, efficiency, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a BSCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

A minimum five‐component five‐term single‐nonlinearity chaotic jerk circuit based on a twin‐jerk single‐op‐amp technique

A minimum 5‐component 5‐term single‐nonlinearity chaotic jerk circuit is presented as the first simplest chaotic jerk circuit in a category that a single op‐amp is employed. Such a simplest circuit displays 5 simultaneous advantages of (1) 5 minimum basic electronic components, (2) 5 minimum algebraic terms in a set of 3 coupled first‐order ordinary differential equations (ODEs), (3) a single minimum term of nonlinearity in the ODEs, (4) a simple passive component for nonlinearity, and (5) a single op‐amp. The proposed 5‐term single‐nonlinearity chaotic jerk circuit and a slightly modified version of an existing 6‐term 2‐nonlinearity chaotic jerk circuit form mirrored images of each other. Although both mirrored circuits yield 2 different sets of the ODEs, both sets however can be recast into a pair of twin jerk equations. Both mirrored circuits are therefore algebraically twin 5‐component chaotic jerk circuits, leading to a twin‐jerk single‐op‐amp approach to the proposed minimum chaotic jerk circuit. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results. Dynamical properties are also presented.