Designing a novel high-performance FPGA architecture for data intensive applications

A wide variety of real-time applications (e.g. multimedia, communication, etc.) require implementations that meet tight timing constraints. This work introduces novel high-performance FPGA architecture capable of implementing efficiently any time critical application. The fundamental contribution of the proposed reconfigurable architecture is the design of a highly efficient (performance and power consumption) interconnection structure, taking into consideration the statistical and spatial data extracted from applications, which are implemented on Virtex FPGAs. The derived architecture is software-supported by the MEANDER design framework. Using a number of real-time applications, extensive comparison study in terms of several design parameters proves the effectiveness of the proposed architecture against to Virtex one. More specifically, the proposed architecture achieves performance improvement and power savings up to 20 and 16%, respectively. Moreover, compared to a Virtex architecture with same power budget, our architecture achieves performance improvement by 42%.

A framework for rapid evaluation of heterogeneous 3-D NoC architectures

The scalability of communication infrastructure in modern Integrated Circuits (ICs) becomes a challenging issue, which might be a significant bottleneck if not carefully addressed. Towards this direction, the usage of Networks-on-Chip (NoC) is a preferred solution. In this work, we propose a software-supported framework for quantifying the efficiency of heterogeneous 3-D NoC architectures. In contrast to existing approaches for NoC design, the introduced heterogeneous architecture consists of a mixture of 2-D and 3-D routers, which reduces the delay and power consumption with a slight impact on packet hops. More specifically, the experimental results with a number of DSP applications show the effectiveness of the introduced methodology, as we achieve on average 25% higher maximum operation frequency and 39% lower power consumption compared to the uniform 3-D NoCs.     

裸眼3D液晶屏FPGA时序控制技术研究

裸眼3D液晶屏为图像显示载体,可把左右眼的图像准确送至双眼形成立体视觉。左右眼图像信号使用FPGA来准确控制帧同步、行同步与像素时钟,使图像像素准确地传输到屏幕相应位置。研究了裸眼3D屏的数据接口要求,通过裸眼3D显示算法和利用硬件描述语言建立了图像数据流传输模型,得出了裸眼3D字幕显示的可行逻辑设计。系统经过实验验证,运行稳定。     

A survey of memory architecture for 3D chip multi-processors

3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and the parallelism of CMPs, which are emerging as active research topics in VLSI and multi-core computer architecture communities. One significant potentiality of 3D CMPs is to exploit the diversity of integration processes and high volume of vertical TSV bandwidth to mitigate the well-known “Memory Wall” problem. Meanwhile, the 3D integration techniques are under the severe thermal, manufacture yield and cost constraints. Research on 3D stacking memory hierarchy explores the high performance and power/thermal efficient memory architectures for 3D CMPs. The micro-architectures of memories can be designed in the 3D integrated circuit context and integrated into 3D CMPs. This paper surveys the design of memory architectures for 3D CMPs. We summarize current research into two categories: stacking cache-only architectures and stacking main memory architectures for 3D CMPs. The representative works are reviewed and the remaining opportunities and challenges are discussed to guide the future research in this emerging area.     

FPGA的3D视频前端处理与显示系统设计

针对目前国内3D电视芯片的缺少而导致3D片源短缺,传统视频处理过程复杂,以及红蓝3D视频观看时出现重影、亮度降低等问题,本文设计了一款基于FPGA的3D视频前端处理与显示系统。以两路摄像头采集的信号作为输入源,采用Altera公司的Cyclone IV系列FPGA芯片为处理核心,实时地完成数据采集和图像处理,采用LCOS微显示器件作为显示单元,得到了效果逼真的3D视频图像。     

5/3小波提升结构的深度流水线优化*

为了满足基于小波变换的高速信号实时处理的需求,在FPGA上实现更高速的5/3小波变换。采用静态时序分析的方法分析了当前5/3小波变换结构中影响速度的主要因素,并采用深度流水线技术切断原结构中存在的较长组合逻辑路径,从而提高了最高工作频率。使设计中仅增加少量寄存器开销便可获得原结构250％的速度,最高可实现每秒300M样本的数据吞吐量,可用于设计基于小波变换和FPGA的高速信号处理系统。     

PDM平台上的三维CAD通用集成框架

构建了PDM和三维CAD软件集成的基本模型和集成框架。该框架通过一致的数据模型,能够灵活地集成不同的三维CAD系统和PDM系统。在数据模型的表达上,采用了XML这种流行的易于扩展的技术方法;在集成框架设计上,采用了抽象工厂等成熟的设计模式,并提供了标准化的接口定义来扩展集成框架的功能。文章对集成框架的功能和具体实现方法进行了论述。     

Multistage A2LVQ architecture and implementation for image compression

This paper presents the implementation of two hardware architectures, i.e., A₂ Lattice Vector Quantization (LVQ) and Multistage A₂LVQ (MA₂LVQ), using a Field-Programmable Gate Array (FPGA). First, the renowned LVQ quantizer by Conway and Sloane is implemented followed by a low-complexity A₂LVQ based on a new A₂LVQ algorithm. It is revealed that the implementation requires high number of multiplier circuits. Then the implementation of a low-complexity A₂LVQ is presented. This implementation uses only the first quadrant of the A₂ lattice Voronoi region formed by W and T regions. This paper also presents the implementation of a multistage A₂LVQ (MA₂LVQ) with an architecture built from successive A₂ quantizer blocks. Synthesis results show that the execution time of the low-complexity A₂LVQ reaches up to 35.97 ns. The MA₂LVQ is implemented using both low-complexity A₂LVQ and ordinary A₂ architectures. The system with the former architecture utilizes less logic and register elements by 47%.     

Slice coherence in a query-based architecture for 3D heterogeneous printing

We report on 3D printing of artifacts with a structured, inhomogeneous interior. The interior is decomposed into cells defined by a 3D Voronoi diagram and their sites. When printing such objects, most slices the printer deposits are topologically the same and change only locally in the interior. The slicing algorithm capitalizes on this coherence and minimizes print head moves that do not deposit material. This approach has been implemented on a client/server architecture that computes the slices on the geometry side. The slices are printed by fused deposition, and are communicated upon demand.     

SM3哈希算法的硬件实现与研究

随着信息社会的进一步发展,哈希算法作为保护信息完整性的重要密码算法,它的应用越来越广泛。美国NIST组织已经顺利完成了哈希算法标准SHA0,SHA1和SHA2的征集工作,并且SHA-3的征集工作将于2012年结束。SM3作为国内商业应用中的国家标准哈希算法,于2010年12月公开。本文在硬件平台FPGA上实现了高吞吐率的SM3,经过优化处理SM3在Xilinxv5平台上的吞吐率可以达到1．5Gbps左右,并且就SM3在FPGA上的效率和SHA1,SHA2以及SHA-3的候选算法BLAKE在FPGA平台上的效率做了比较和分析。     

AVS 3D实时解码器在FPGA/SoC平台上的设计与实现

AVS(audio video coding standard)工作组针对3D视频提出了双目立体视频编解码方案。以AVS双目拼接算法为核心,通过FPGA硬件加速模块完成双目立体ES流的语法元素解析,与So C开发板Xilinx ZYNQ 7020协同工作,创新性地在FPGA/So C协同平台上实现了AVS 3D实时解码器。通过HDMI接口将解码数据输出到三维显示设备,得到了具有深度信息的3D视频,验证了AVS 3D实时解码器的有效性。     

中国古建筑蕴含的现代设计特征及三维CAD 方法研究

论文涉及中国古建筑梁架结构中蕴含的类似现代工业产品设计的理念与方 法,包括零件——装配体设计、模数化设计和系列化设计的理念与方法,论文还涉及利用三 维CAD 手段表达中国古建筑设计的研究。     

基于嵌入式Linux和FPGA的数据通信系统设计

针对嵌入式系统在数据采集和智能控制领域的应用需求,设计并实现了一种基于嵌入式Linux的S3C2440A处理器和FPGA的数据通信系统。介绍了FPGA中总线接口设计和ARM-Linux下的驱动程序设计,并给出了部分源代码和测试方法。测试结果表明,该系统成本低,功能完善,运行稳定,在实际工程应用中具有一定的价值。     

原位根系三维构型测量系统的设计与实现

为定量描述和分析三维根系构型,设计开发了植物根系三维构型测量分析系统,以实现原位根系的三维可视化,以及检测、分析其三维构型参数的功能。系统实现了对原位根系CT序列图像读写、分割、三维重建、三维矢量模型构建等关键算法,并在此基础上完成三维根系构型参数自动检测。通过对原型系统进行初步的测试与分析,初步实现了根系三维构型参数的自动化测量并获得了较好的测量结果。     

利用组件技术开发三维标准件库

针对国内大多数三维标准件库存在的CAD／CAM平台依附性强的缺陷，以COM技术为基础，采用Windows DNA结构，将不同平台标准件库中的重复部分提取出来，以核心组件群的方式表示，并在这个组件群的基础上提出一个面向多个三维造型平台的标准件库系统的解决方案。     

一种基于三维Delaunay三角化的曲面重建算法

提出一种基于三维Delaunay三角化的区域增长式曲面重建方法。该方法以空间点云的Delaunay三角化为基础,结合局部区域增长的曲面构造,较以往方法具有人为参与更少、适用范围更广的优点。算法采用增量式插入点的方式构建空间Delaunay划分,采用广度优先算法,以外接圆最小为准则从Delaunay三角化得到的四面体中抽取出合适的三角片构成曲面。该算法的设计无须计算原始点集的法矢,且孔洞系数对重建的结果影响很小,重建出的三角网格面更符合原始曲面的几何特征。无论待建曲面是否是封闭曲面,本算法均可获得较好的重建效果。     

基于FPGA的DDR3存储控制的设计与验证

DDR3SDRAM是第三代双倍数据传输速率同步动态随机存储器,DDR3具有高速率、低电压、低功耗等特点[1-2];在DDR3控制器的实际使用中,如何将用户需要存储的数据在DDR3中快速存储非常重要,如果数据被送到DDR3接口的速度低,则会影响DDR3的存储速度,同时影响DDR3的实际应用,因此,针对DDR3存储器设计存储控制有重要的意义[2];基于此设计主要分为低速读写控制与高速流读写控制,低速读写控制主要用于小数据量的操作,高速流读写控制主要用于批量数据的存储操作;此设计在FPGA上通过了大量数据读写的验证,证明数据存储的正确性;经过测试,在高速流读写模式下,DDR3存储控制设计的带宽利用率最大为66.4%;此设计在功能和性能上均符合系统总体设计的要求。     

组件式3D-UGIS及关键技术研究

论文分析了3D-UGIS和组件式GIS的特点,提出组件式3D-UGIS的系统构架方式,并给出基本结构。文章以深圳市建筑物信息动态管理系统开发为例,详细说明了基于组件的3D-UGIS开发的关键技术。与其他3D-GIS系统相比,组件式3D-UGIS在系统开发、扩展和实用性方面具有优势。     

基于FPGA的MP3音乐播放器设计

系统实现了基于FPGA的MP3音乐播放器的设计,详细介绍了系统的硬件组成和软件设计组成,并只对设计中的两个难点即控制器模块和发声模块的设计进行了详细说明,给出了相关流程图和部分代码,有利于读者对MP3音乐播放器设计进行深入了解。     

3-D model building for computer vision

This paper presents a Computer-Aided Geometric Design (CAGD) based approach for building 3-D models. A new method is given which allows the points on the surface of the designed object to be sampled at the desired resolution. The resulting data structure includes 3-D coordinates of the points, surface normals and neighborhood information.