Voltage controlled oscillators using complementary current mirror inverter

Complementary current mirror inverters have large bandwidth, small time delay but small gain whereas complementary inverters have high gain but large time delay. Ring oscillators have been realised using a combination of both types of inverter to achieve stable high frequency oscillation. Voltage controlled oscillators were obtained by tuning the frequency of oscillation with supply voltage.<>     

High temperature performance of NMOS integrated inverters and ringoscillators in 6H-SiC

Electrical characterization up to 573 K is performed on integrated inverters with different beta ratios and 17-stage ring oscillators based on SiC NMOS technology. These devices are fabricated on a p-type 6H-SiC epitaxial layer with a doping concentration of N_A=1·10 ¹⁶ cm^-3. The n⁺ source/drain regions and buried channels for depletion-mode load transistors are achieved by ion implantation of nitrogen. Direct current measurements of the inverters with a 5 V power supply yield proper output levels and acceptable noise margins both at 303 and 573 K. Dynamic measurements with square waves show the full voltage swing up to 5 kHz in this temperature range. The 17-stage ring oscillators, driven by a 5.5 V power supply, show an oscillator frequency of 625 kHz at 303 K, which corresponds to a 47 ns delay per inverter stage. This time constant increases only to 59 ns at 573 K. The temperature drift of the measured output signal is well below 30% up to this elevated temperatures. During 20 heat cycles up to 573 K in air, no measurable drift in circuit parameters occurred. In addition, only a slight dependence of the oscillator frequency on supply voltage is observed     

A power-efficient wide-range phase-locked loop

This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors' sizes rather than operating frequencies. By applying the TSMC 0.35-μm CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations     

Demonstration of sub-5 ps CML ring oscillator gate delay withreduced parasitic AlInAs/InGaAs HBT

We have demonstrated a gate delay of 4.9 ps and a power dissipation of 8 mW per CML inverter in an AlInAs-InGaAs HBT technology with 150 mV logic swing. The demonstration circuit was a 15-stage ring oscillator based on CML inverters with a fan-out of 1 and a nominal 3.1 V supply. The same circuit was measured to have a gate delay of 4.7 ps and a power dissipation of 13 mW per inverter using a 3.6 V supply, and a gate delay of 6.2 ps and a power dissipation of 2.4 mW per inverter with a 2.2 V supply. These are the fastest results for a bipolar transistor based logic family in any semiconductor and comparable to the fastest results for any logic family in any semiconductor. Because two gate delays are required for the simplest useful sequential logic circuits such as clocked flip-flops, this is a significant milestone in that it is the first, though somewhat idealized, demonstration that logic at 100 GHz is realizable in InP-based HBT     

An accurate approach of nonlinearity compensation for VSI inverter output voltage

An accurate nonlinearity compensation technique for voltage source inverter (VSI) inverters is presented in this paper. Because of the nonlinearity introduced by the dead time, turn-on/off delay, snubber circuit and voltage drop across power devices, the output voltage of VSI inverters is distorted seriously in the low output voltage region. This distortion influences the output torque of IM motors for constant V/f drives. The nonlinearity of the inverter also causes 5th and 7th harmonic distortion in the line current when the distributed energy system operates in the grid-connected mode, i.e., when the distributed energy system is parallel to a large power system through the VSI inverter. Therefore, the exact compensation of this nonlinearity in the VSI inverter over the entire range of output voltage is desirable. In this paper, the nonlinearity of VSI inverter output voltage and the harmonic distortion in the line current are analyzed based on an open-loop system and a L-R load. By minimizing the harmonic component of the current in a d-axis and q-axis synchronous rotating reference frame, the exact compensation factor was obtained. Simulations and experimental results in the low frequency and low output voltage region are presented.     

1μm栅HEMT DCFL门电路及环形振荡器的设计与实验研究

利用作者提出的HEMT DCFL倒相器直流传输特性及瞬态特性计算机分析的模型,设计并制成了HEMT DCFL门电路及环形振荡器.在电路设计中,重点讨论了E/D NEMT倒相器的电路性能与器件的主要参数(栅长、栅宽、阈压)间的理论关系.工艺研究中,建立了挖栅时沟道饱和电流Is′与阈压值V_(t~h)间关系的理论曲线,并改进了传统化学湿法刻蚀工艺的阈压均匀性及E,D器件电流匹配的控制精度.实验制作了栅长为1μm的增强型和耗尽型HEMT.在1×1mm范围内,阈压偏差小于50mV,E/D倒相器的传输特性为:V_(OH)≈V_(DD),V_(OL)<0.1V,高、低电平转换范围仅0.1V,噪容达0.3V左右.研制的9级、17级环形振荡器,在V_(DD)为0.5V到3.5V范围内都观察到正弦波振荡波形.     

Switching characteristics of scaled CMOS circuits at 77 K

Performance enhancement of CMOS inverters at room and liquid-nitrogen temperatures are studied. The extent of delay improvement at low temperature is limited by the velocity saturation effect, as the channel lengths are decreased and/or the supply voltage increased. An analytical delay model taking into account velocity saturation is developed that accurately predicts the measured delay of CMOS inverter chains with drawn channel lengths down to 0.5 µm, Compared are the relative merits of CMOS devices operating at 77 K and those scaled for room-temperature operations.     

A Multilevel Inverter Topology for Inductively Coupled Power Transfer

This paper describes a multilevel inverter that can synthesize quantized approximations of arbitrary ac waveforms. This converter could be used to deliver power over multiple frequencies simultaneously. Unlike traditional multilevel inverters, this topology does not require an external voltage balancing circuit, a complicated control scheme, or isolated dc sources to maintain its voltage levels while delivering sustained real power. In this paper, we use this circuit for heating frequency selectable induction targets designed to stimulate temperature sensitive polymer gel actuators. For this application our multilevel inverter offers higher efficiency than a pulse width modulated full-bridge inverter (a more conventional power supply solution) at comparable levels of total harmonic distortion     

Power electronics in German railway propulsion

The state of the art of power electronics is reviewed. Because of the different requirements, such as suburban or long distance traffic and DC or AC supply, various systems are in use and some peculiar configurations, as resistor braking, have become important. With AC supply special line-commutated rectifiers causing low displacement factor and small harmonic content are used for DC motor propulsion. With DC supply choppers allow nondissipative motor control, often combined with special circuits for field weakening and for change of driving/breaking. Particularly important is three-phase propulsion with robust squirrel-cage motors, made possible by the development of suitable variable-frequency inverters. Both current source and voltage source inverters are used in suburban cars as well as for locomotive drives. The most universal but also most complicated system served by the voltage source inverter is described in more detail     

基于重复控制和无差拍控制的逆变电源数字控制技术研究

随着DSP技术的发展，数字控制在逆变电源控制领域的应用受到人们的关注。逆变电源中因非线性负载等因素引起的干扰具有周期性，而这些干扰导致输出波形的畸变具有重复性，采用重复控制策略可以消除输出电压谐波，但该控制方法的动态响应慢。无差拍控制具有瞬时响应快，精度高等特点。文中将重复控制和无差拍控制相结合用于逆变电源数字控制系统中，得到更为完善的逆变电源控制策略。仿真结果表明，由该方法设计的控制器用于逆变电源系统具有输出波形好，动态响应快，适应负载的能力强等优点。     

Design and performance of GaAs normally-off MESFET integrated circuits

DC and transient analyses of GaAs normally-off MESFET integrated circuits are described. The design tradeoffs between device parameters and logic characteristics are discussed for an inverter with a resistive load. By increasing the supply voltage to several times that of the built-in voltage, the propagation delay time can be lowered similar to that when using an active load (current source). To investigate the speed-power performance of the IC's, ring oscillators with different fan-in and fan-out configurations were fabricated. A binary frequency divider which uses a master-slave flip-flop was tested. The maximum counting frequency of the divider was 610 MHz at a supply voltage of 1.5 V. This coincides with the results obtained from the ring oscillators with fan-in/fan-out = 2/2. Comparing the experimental results with the theory, the effective electron mobility in the thin channel layer is expected to be very low. By improving the mobility and shortening the gate length to half a micrometer, practical functioning circuits should operate with an average propagation delay time of less than 100 ps.     

Three-Level Inverter Scheme With Common Mode Voltage Elimination and DC Link Capacitor Voltage Balancing for an Open-End Winding Induction Motor Drive

A dc link capacitor voltage balancing scheme along with common mode voltage elimination is proposed for an induction motor drive, with open-end winding structure. The motor is fed from both the ends with three-level inverters generating a five level output voltage space phasor structure. If switching combinations, with zero common mode voltage in the pole voltage, are used, then the resultant voltage space vector combinations are equivalent to that of a three-level inverter. The proposed inverter vector locations exhibit greater multiplicity in the inverter switching combinations which is suitably exploited to arrive at a capacitor voltage balancing scheme. This allows the use of a single dc link power supply for the combined inverter structure. The simultaneous task of common mode voltage elimination with dc link capacitor voltage balancing, using only the switching state redundancies, is experimentally verified on a 1.5-kW induction motor drive     

Decoupling Control Strategy for Single Phase SPWM Parallel Inverters

A deconpling control strategy of inverter parallel system is proposed based on the equivalent output impedance of single phase voltage source SPWM （sinusoidal pulse width modulation） inverter. The active power and reactive power are calculated in terms of output voltage and current of the inverter, and sent to the other inverters in the parallel system via controller area network （CAN） bus. By calculating and decoupling the circumfluence of the active power and reactive power, the inverters can share load current via the regulation of the reference-signal phase and amplitude. Experimental results of an 110V/2kVA inverter parallel system show the feasibility of the decoupling control strategy.     

PWM methods to handle time delay in digital control of a UPS inverter

With the popularity of micro-processors, digital controllers are widely used in uninterruptible power supply (UPS) inverters. These digital control systems of UPS inverters require a time interval for sampling and computation, which sometimes affects the performance of inverters. In this paper, the problem of time delay in digital control of a UPS inverter is discussed. Then two novel pulsewidth modulation (PWM) methods, the two-polarity PWM method and the asymmetric PWM method, are proposed to handle the time-delay problem. Both of these PWM methods can achieve a wide range of duty ratio between 0.05-0.95, which is independent of inverter model. Furthermore, they are easy to implement using a digital micro-controller. Experimental results are presented in the paper to verify feasibility of the proposed PWM methods.     

Small-signal analysis of a low-cost power control for LCC series-parallel inverters with resonant current mode control for HID lamps

In this paper, a low-cost power control for LCC series-parallel inverters with resonant current mode control for high intensity discharge (HID) lamps is presented. These resonant inverters require controlling the power supplied to the lamp in order to avoid exceeding the maximum lamp power recommended by the lamp manufacturer. The classical control method measures the lamp voltage and current and they are multiplied analogically, obtaining the lamp power consumption measure. This control circuitry results very complex due to the lamp voltage and current wide variations range during ignition and discharge processes. Assuming a regulated input dc voltage (bus voltage) provided by the power factor correction (PFC) pre-regulator and an inverter constant efficiency along the lamp aging, the lamp power consumption may be estimated and regulated properly measuring the inverter average input current. Also, the small-signal analysis performed allows obtaining the small-signal resonant inverter input impedance and studying the connection stability between PFC pre-regulator and inverter. The inverter small-signal analysis has been performed and an electronic ballast prototype for 250-W HPS lamps has been implemented and tested verifying the low-cost lamp power control method proposed.     

具有提升直流环节稳态电压功能的单相全桥 谐振直流环节逆变器

为改善直流电压利用率,提出了一种具有提升直流环节稳态电压功能的单相全桥谐振直流环节软开关逆变器,利用辅助电路中的变压器可以将电能补充到直流母线上等效为电压源的钳位电容,使直流环节稳态电压高于直流电源电压,提高了逆变器输出线电压的基波幅值和直流电压利用率.文中分析了电路的工作状态.在4kW样机上的实验结果表明逆变器的主开关和辅助开关能完成软切换.因此,该拓扑结构对于研发高性能谐振直流环节逆变器具有一定的借鉴意义.     

单相光伏并网逆变器控制策略研究与设计

针对光伏并网逆变器并网后其本质上为电流源的特点,采用STM32F103VET6型ARM芯片作为系统的控制核心,制造了一台5 kW单相光伏并网型逆变器。采用了固定开关频率的电流瞬时值控制技术来实现对并网电流的控制,在控制策略中加入了电压前馈来抑制电网电压对逆变器输出电流的影响,使用二阶电流预估来抵消SPWM波形延时对系统控制的影响。并且优化了最大功率点跟踪（MPPT）。实验证明,该逆变器样机性能完全达到设计要求。     

Novel resonant pole inverter for brushless DC motor drive system

The brushless dc motor (BDCM) has been widely used in industrial applications because of its low inertia, fast response, high power density, high reliability, and maintenance-free reputation. It is usually supplied by a hard-switching pulse width modulation inverter, which normally displays relative low efficiency since the power losses across the switching devices are high. In order to reduce the losses, many soft switching inverters have been designed. However, these inverters have such disadvantages as high device voltage stress, large dc link voltage ripple, discrete pulse modulation, and complex control scheme. This paper introduces a novel resonant pole inverter, which is unique to a BDCM drive system, and is easy to implement. The inverter possesses the advantages of low switching power loss, low inductor power loss, low device voltage stress, and simple control scheme. The operation principle of the inverter is analyzed. Simulation and experimental results are proposed to verify the theoretical analysis.     

Control of cascaded multilevel inverters

A new type of multilevel inverter is introduced which is created by cascading two three-phase three-level inverters using the load connection, but requires only one dc voltage source. This new inverter can operate as a seven-level inverter and naturally splits the power conversion into a higher-voltage lower-frequency inverter and a lower-voltage higher-frequency inverter. This type of system presents particular advantages to Naval ship propulsion systems which rely on high power quality, survivable drives. New control methods are described involving both joint and separate control of the individual three-level inverters. Simulation results demonstrate the effectiveness of both controls. A laboratory set-up at the Naval Surface Warfare Center power electronics laboratory was used to validate the proposed joint-inverter control. Due to the effect of compounding levels in the cascaded inverter, a high number of levels are available resulting in a voltage THD of 9% (without filtering).     

Full binary combination schema for floating voltage source multilevel inverters

This paper presents schema of operation for floating voltage source multilevel inverters. The primary advantage of the proposed schema is that the number of voltage levels (and thus power quality) can be increased for a given number of semiconductor devices when compared to the conventional "flying capacitor" topology. However, the new schema requires fixed floating sources instead of capacitors and therefore is more suitable for battery power applications such as electric vehicles, flexible AC transmission systems and submarine propulsion. Alternatively transformer/rectifier circuits may be used to supply the floating sources in a similar way to cascaded H-bridge inverters. Computer simulation results are presented for 4-level, 8-level, and 16-level inverter topologies. A 4-level laboratory test verifies the proposed method.