Effects of oxidation on reliability of screen-printed silver circuits for radio frequency applications

High reliability has become one of the crucial requirements for portable electronic devices, due to the high dependence of their radio frequency (RF) characteristics on the end-user's surroundings. The RF characteristics of screen-printed silver (Ag) circuits were investigated after a steady-state temperature and humidity storage test. A conductive paste containing Ag nanoparticles was screen-printed onto a silicon (Si) substrate and then sintered at 250 °C for 30 min in air. The printed Ag circuits were placed in a chamber at 85 °C/85% relative humidity (RH) for various durations: 100, 300, 500, 1000 h. The microstructural evolution and thickness profiles of the Ag circuits were observed with field emission scanning electron microscopy and α-step, respectively. The oxidation of the printed Ag circuit surface was analyzed with Auger electron spectroscopy. A network analyzer and Cascade's probe system in the frequency range of 40 MHz to 40 GHz were employed to measure the scattering parameters of the Ag circuits. The experimental results showed that the insertion losses at higher frequencies increased with increasing durations of exposure to the 85 °C/85% RH environment, due to the thicker specific layer for oxidation on the circuit surfaces. The oxide layer was the dominant factor affecting the RF characteristics of the screen-printed Ag thin circuits. Therefore, it is essential to control the oxidation of printed circuits for versatile RF applications.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

Optical Fiber Technique for Remote Stabilization of RF Phase

We demonstrate an optical-fiber-based technique to deliver a radio-frequency reference phase to a remote location. Using a reflected portion of the RF amplitude-modulated optical signal from the remote location in a feedback loop, we show that the remote phase can be kept within ± 0.3° of the desired value, independent of temperature variations along a fiber length of 2 km or more. The instrument is designed to operate at 416 MHz, and works satisfactorily over a ± 10% RF bandwidth. In addition, an automatic phase ranging circuit allows the device to maintain phase stabilization over an infinite number of phase cycles. The system is presently being installed at the Molonglo Observatory Synthesis Telescope near Canberra, Australia.     

Utility of RF MEMS miniature switched capacitors in phase shifting applications

This paper demonstrates research carried out towards the development of switched capacitors having miniature dimensions. Such devices are based on the Radio Frequency Micro Electro Mechanical Systems (RF MEMS) technique which has gained prominence in implementing a wide variety of microwave and millimetre devices till date. Switched capacitors having standard or conventional dimensions are prone to several limitations which are addressed by scaling down the standard dimensions by 150× times (in terms of area requirement). Such switched capacitors are employed to develop phase shifters working in K-band (22 GHz) frequency range to yield appreciable performance both in terms of electromechanical and RF characterizations. Such switched capacitors are utilized to develop phase shifters which find immense applications in the design of Phased Array RADARs. Switched capacitors fabricated on 500 µm thick quartz substrates, result in 30° phase shift (0.66 mm × 1 mm in dimension) with associated minimum −0.18 dB insertion loss and better than −21 dB reflection coefficient at 22 GHz frequency. Electromechanical characterization reports an actuation voltage of 14.6 V, mechanical vibration frequency of 2.5 MHz and a switching time of 620 ns respectively. Demonstrations showing complete realization of 180° phase shifter (4 mm × 1 mm) employing a cascaded arrangement of six similar 30° unit cells are also included in this paper.     

Design and implementation of micro-power temperature to duty cycle converter using differential temperature sensing

The CMOS based temperature detection circuit has been developed in a standard 180 nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30 °C to +70 °C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15 °C to +0.35 °C. Similarly, CTAT generator has mean temperature accuracy of ±1 °C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18 mV/°C with the temperature inaccuracy of ±1.3 °C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5 °C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2 μW.     

A compact broadband MMIC sub-harmonic mixer using quasi-lumped transmission lines

A compact broadband monolithic microwave integrated circuit (MMIC) sub-harmonic mixer using an OMMIC 70 nm GaAs mHEMT technology is demonstrated for 60 GHz down-converter applications. The present mixer employs an anti-parallel diode pair (APDP) to fulfill a sub-harmonic mixing mechanism. Quasi-lumped components are employed to broaden the operational bandwidth and minimize the chip size to 1.5×0.77 mm². The conversion gain is optimized by a quasi-lumped 90° phase shift stub. Experimental results show that from 50 GHz to 70 GHz, the conversion gain varies between −12.1 dB and −15.2 dB with a LO power level of 10 dBm and 1 GHz IF. The LO-to-RF, LO-to-IF and RF-to-IF isolations are found to be greater than 19.5 dB, 21.3 dB and 25.8 dB, respectively. The second harmonic component of the LO signal is suppressed. The proposed mixer has an input 1 dB compression point of -2 dBm and exhibits outstanding figure-of-merits.     

Single-grain Si thin-film transistors SPICE model,analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350 °C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 μm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f_T, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

Reliability of 100 nm AlGaN/GaN HEMTs for mm-wave applications

The effect of gate metallization and gate shape on the reliability and RF performance of 100 nm AlGaN/GaN HEMTs on SiC substrate for mm-wave applications has been investigated under on-state DC-stress tests. By replacing the gate metallization from NiPtAu to PtAu the median time to failure at T_ch = 209 °C can be improved from 10 h to more than 1000 h. Replacing the PtAu T-gate by a spacer gate further reduces the degradation rate under on-state stress, but decreases the current-gain cut-off frequency from 75 GHz to 50 GHz. Physical failure analysis using electroluminescence and TEM cross-section revealed pit and Ni void formation at the gate foot as the main degradation mechanisms of devices with NiPtAu T-gate. High resolution EDX mapping of stressed devices indicates that the formation of pits is caused by a local aluminium oxidation process. Simulation of the stress induced changes of the input characteristics of devices with NiPtAu gate further proves the formation of pits and Ni voids.     

High linearity,low power RF mixer design in 65 nm CMOS technology

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.     

Design of novel wideband reflective phase shifters with wide range of phase applications

This paper presents wideband compact differential reflective phase shifter based on the double layer slot-coupled coupler configuration. This novel phase shifter arrangement consists of a 3-dB hybrid coupler with the coupled and transmission ports terminated with rectangular and elliptically shaped microstrip loads. By altering the ports termination of the coupler, phase shifters propose differential phase ranging from −90° to +90° over 1.3–5.9G Hz frequency band. To achieve different range of phase performance, the proper reactance is calculated at the outputs of coupler. These reactances are transformed to the elliptical or rectangular-shaped microstrip load with various dimensions for every phase shifter. The calculation and simulations results show that the developed circuits could provide ±30°, ±60°, ±45° and ±90° differential phase shifts. For verification of this wideband phase shifter design method, two phase shifter example with rectangular and elliptical load termination is fabricated and measured. The measured return loss of the phase shifter with elliptically load is better than 10 dB over 1.3–5.9G Hz frequency band as well as insertion loss is less than 1 dB. The phase shift deviation is less than 2.1°. The results demonstrate that the proposed phase shifters are well suited for use in GPS/LTE/WiMax/WLAN frequency bands.     

A ±3.07% frequency variation clock generator implemented using HV CMOS process

In this paper, we propose a clock generator with a feedback TPC (temperature and process compensation) bias circuit fabricated by a high-voltage (HV) CMOS process. Particularly, the feedback TPC bias is composed of an OPA, MOS transistors and resistors, where large BJT devices are no longer needed such that it is easy to be integrated on chip with small area overhead. The feedback TPC bias circuit, including a MOS transistor, four resistors, and a differential amplifier, is used to provide temperature and process compensation. The proposed circuit design is implemented using 0.25 μm 60 V BCD process. Measurement of 10 dies in the range of 0 °C to 100 °C is carried out to verify that the worst frequency drifting error is ±3.07%.     

Thermoelectrical modelling and simulation of devices based on VO2

Limits of development of conventional silicon-based integrated circuits get closer. More and more effort is done to develop new devices for integrated circuits. A promising structure is based on the semiconductor-to-metal phase change of vanadium-dioxide at about 67 °C. In these circuits the information is carried by combined thermal and electrical currents. For device modelling and circuit design, accurate distributed electro-thermal transient simulation is mandatory. This paper is the first one to present an electro-thermal transient simulation method for VO₂ devices operating in real-world conditions. The paper presents three VO₂ material models, the algorithmic extension of an electro-thermal field simulator to be able to handle hysteresis and the transient simulation issues of VO₂ and the modelling of VO₂ based devices. The paper compares measured and simulated device characteristics.     

Determination of the average channel temperature of GaN MOSHFETs under continuous wave and periodic-pulsed RF operational conditions

We present a method to determine the average device channel temperature of AlGaN/GaN metal–oxide–semiconductor heterostructure field effect transistors (MOSHFETs) in the time domain under continuous wave (CW) and periodic-pulsed RF (radiation frequency) operational conditions. The temporal profiles of microwave output power densities of GaN MOSHFETs were measured at 2 GHz under such conditions and used for determination of the average channel temperature. The measurement technique in this work is also being utilized to determine the thermal time constant of the devices. Analytical temporal solutions of temperature profile in MOSHFETs are provided to support the method. The analytical solutions can also apply to generic field effect transistors (FETs) with an arbitrary form of time-dependent heat input at the top surface of the wafer. It is found that the average channel temperature of GaN MOSHFETs on a 300 μm sapphire substrate with the output power of 10 W/mm can be over 400 °C in the CW mode while the average channel temperature of GaN MOSHFETs on a SiC substrate with the same thickness only reaches 50 °C under the same condition. The highest average channel temperature in a pulsed RF mode will vary with respect to the duty cycle of the pulse and type of the substrate.     

A RF front-end for DVB-SH based on current conveyors

Inductors are used extensively in Radio Frequency Integrated Circuits to design matching networks, load circuits of voltage controlled oscillators, filters, mixers and many other RF circuits. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this paper a new methodology for designing the RF frontend necessary for the DVB-SH in a 90 nm CMOS technology based on the use current conveyors (CC) is presented. The RF frontend scheme is composed of a second generation CC (CCII) LNA with asymmetric input and output, an asymmetric to differential converter, and a passive differential mixer followed by two CCII transimpedance amplifiers to obtain a high gain conversion. Measurements show a conversion gain of 20.8 dB, a 14.5 dB noise figure, an input return loss (S11) of −14.3 dB and an output compression point of −3.9 dBm. This combination draws 28.4 mW from a ±1.2 V supply.     

Life test of an X-band MMIC multi-function chip for active phased array radar applications

A 1000-h steady state life test at a temperature of 125 °C was performed on ten X-band MMIC multifunction chips for use in active phase array radar systems. Internal switches, phase shifters, and attenuators were operated through an integrated serial-to-parallel converter under the five-second stepped external control signal for the life test period. None of the ten samples failed under the failure criteria based on the JEP118 standard. The calculated failure rate using the Chi Square Statistic was 1.6 e⁻⁶ failures/h for the 90% confidence level. Maximum DC current variation was +16% for an initial value. Maximum variations of small signal gain, phase shift, and attenuation were 0.96 dB, 2°, and 0.17 dB, respectively, over a frequency range of 8.5–10.5 GHz.     

Effect of annealing on photoluminescence of passivated porous silicon

Photoluminescence (PL) of annealed porous silicon (PS) without and with nitrogen passivation has been investigated. The un-nitridated PS emits intense blue and green light, while that with passivation, emits only blue light and its intensity increases obviously. It is found that the PL intensity of the nitrified PS decreases with increasing temperature from 300 °C to 700 °C, but increases drastically after annealing at 800 °C and 900 °C, which might be due to the formation of Si–N bonds that passivates the non-radiative centers (Si dangling bonds) on the surface of PS samples. However, the intensity of the un-nitridated PS decreases continuously with increasing temperature from 300 °C to 900 °C, which might be due to desorption of hydrogen.     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications

This paper presents a Sub-mW differential Common-Gate Low Noise Amplifier (CGLNA) for ZigBee standard. The circuit takes the advantage of shunt feedback and Dual Capacitive Cross Coupling (DCCC) to reduce power consumption and the bandwidth extension capacitors to support 2.4 GHz ISM band. An amplifier employing these techniques has been designed and simulated in 0.18 µm TSMC CMOS technology. The Simulation results show a gain of 18.2 dB, an IIP3 of −4.32 dBm and a noise figure of 3.38 dB at 2.4 GHz. The proposed LNA consumes only 967 µW from a 1-V supply.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.