加速寿命试验中修正阿伦尼斯加速因子的研究

阿伦尼斯(Arrhenius)加速因子常用于可靠性加速寿命试验(ALT)或环境应力筛选(ESS)的温度应力加速寿命模型中,但事实上Arrhenius方程和由其得出的Arrhenius加速因子之间存在着矛盾.本文首先提出这一矛盾,接着从激活能的定义及物理意义进行分析,说明了引起矛盾的原因,并最终得出修正Ar-rhenius加速因子.     

Modeling early failure in integrated circuit interconnect

A model based on the random electron–atom scattering is developed to characterize the effects of defects and grain sizes on electromigration caused failure in confined sub-micron metal interconnect lines. Our study shows that lines at sub-micron widths with a more uniform microstructure exhibit a greater consistency in time to failure. Taking mean time to failure and dispersion in time to failure as criteria, the simulator predicts that grain sizes in the 0.03–0.05 μm range are optimal for 0.125 μm wide Al alloy lines. We also argue that the early failure mechanism associated with the missing metal defects is eliminated by using a homogeneous, fine-grained material. The uniformity of the structure results in a mono-modal failure distribution and contributes to increasing the built-in reliability of the interconnect lines.     

Modeling of integrated circuit yield loss mechanisms

A yield model suited for application in a yield control system and based on in-line inspections of control wafers containing the corresponding test structures has been proposed. It is shown that the proposed yield model and yield control system can be used for modeling yield loss mechanisms and predicting efficient investments which are required in order to ensure a competitive yield of integrated circuits. An approach for the extraction of chip critical areas associated with the corresponding yield loss mechanism has been described     

Application of the atomic force microscope to integrated circuit failure analysis

In IC research centers over the past two years, the Atomic Force Microscope (AFM) has become a fairly common tool. Nondestructive imaging with nanometer resolution on uncoated samples in ambient conditions is proving to have a wide range of applications in IC research. Also, during this same period important advances have been made in scanning probe microscopy, particularly relating to atomic force probes. AFM technology has now found acceptance in IC manufacturing as well as research.These new advances include: large sample (full wafer) capability, sharper probe tips capable of measuring sidewalls as steep as 15 degrees from the vertical, noncontact topography measurements, frictional-force measurements, and cross-section analysis. True three-dimensional nanometer-scale metrology can now be applied to process control and failure analysis.Some uses and applications to semiconductors are (1) surface roughness measurment of polished silicon wafers for gate oxide performance improvements, (2) surface roughness of deposited layers, (3) grain-size measurement, (4) depth measurement for etcher control, (5) step-height measurement, (6) gate-oxide integrity, (7) deposited layer integrity over lines, (8) monitoring the effectiveness of cleaning steps, (9) cross-section imaging, (10) high-resolution imaging for process inspection, (11) planarization quality, (12) phase-shift mask development, (13) chrome photomasks — defect imaging and sizing, line-edge quality, (14) defect imaging and sizing, and (15) spin-on glass cure and pore-size process studies     

A subnanosecond integrated switching circuit with MESFET's for LSI

Using a simple channel implantation step, the choice of the threshold voltage determines speed and power. Illustrations are given by the example of a 3-input NOR-gate with 1/spl times/5-/spl mu/m/SUP 2/ channel geometry for the switching transistors. A design with dual threshold voltages allowing the optimization of power consumption while keeping subnanosecond propagation delay times is presented and applied to a speed- and power-optimized dual-type MESFET NOR-gate. Examples are presented of experimental d.c. characteristics measured on fabricated samples exhibiting an average power consumption of 150 /spl mu/W. A propagation delay time of 0.8 ns is deduced for a fan-out of 3. This performance is discussed in conjunction with a set of parameters including geometry, technological reproducibility, and circuit design requirements. It appears that geometries of about 1 /spl mu/m lead to the best compromise for fast switching and optimized LSI organization.     

符号化仿真技术用于提高模拟集成电路设计良率

模拟电路对于工艺偏移的敏感性以及设计良率是模拟电路设计师关心的重要问题.由于数值仿真工具的局限性,至今设计界仍缺乏能有效提高电路可靠性与良率的通用设计辅助工具.提出利用符号化仿真器GRASS(Graph Reduction Analog Symbolic Simulator)快速导出频域设计指标关于电路参数的解析表示,并由此用三维立体图示的方式展示设计指标关于电路参数的依赖敏感度,设计者能够直观的判断如何选择合适的参数组合,以降低工艺偏移可能导致的电路性能恶化,从而提高设计良率.实验表明本文提出的方法可以有效地辅助设计者对于电路参数进行准确判断与选择,是一种值得在实际模拟电路设计中使用的辅助方法.     

Investigation of fundamental EMI source mechanisms drivingcommon-mode radiation from printed circuit boards with attached cables

Fundamental EMI source mechanisms leading to common-mode radiation from printed circuit boards with attached cables are presented in this paper. Two primary EMI source mechanisms have been identified: one associated with a differential-mode voltage and another associated with a differential-mode current, both of which result in a common-mode current on an attached cable. These mechanisms can he used to relate printed circuit layout geometries to EMI sources. The two mechanisms are demonstrated through numerical and experimental results, and an example from a production printed-circuit design is presented     

An integrated driving circuit implemented with p-type LTPS TFTs for AMOLED

Based on the technology of low temperature poly silicon thin film transistors (poly-Si-TFTs), a novel p-type TFT AMOLED panel with self-scanned driving circuit is introduced in this paper. A shift register formed with novel p-type TFTs is pro- posed to realize the gate driver. A flip-latch cooperated with the shift register is designed to conduct the data writing. In order to verify the validity of the proposed design, the circuits are simulated with SILVACO TCAD tools, using the MODEL in which the paramete...     

Smart dynamic wavelength equalizer based on an integrated planaroptical circuit for use in the 1550-nm region

A microprocessor-controlled dynamic wavelength equalizer is presented. Th subsystem is based on an integrated optical circuit made in silica and covers a large portion of the usable region of the electromagnetic spectrum for optical fiber transmission (1530-1565 nm). The chip is connected in a software-controlled feedback loop, and with its dynamic range of ~7 dB for each channel, the system is capable of flattening the spectral response of an erbium-doped fiber amplifier to within 0.35-dB peak-to-peak. Insertion loss equals ~8 dB     

A new gate driver integrated circuit for IGBT devices with advanced protections

The aim of this paper is to discuss new solutions in the design of insulated gate bipolar transistor (IGBT) gate drivers with advanced protections such as two-level turn-on to reduce peak current when turning on the device, two-level turn-off to limit over-voltage when the device is turned off, and an active Miller clamp function that acts against cross conduction phenomena. Afterwards, we describe a new circuit which includes a two-level turn-off driver and an active Miller clamp function. Tests and results for these advanced functions are discussed, with particular emphasis on the influence of an intermediate level in a two-level turn-off driver on overshoot across the IGBT.     

二维寄生电容参数的对偶离散几何法提取

寄生电容参数提取是集成电路领域的关键课题,也是典型的静电场问题之一。通过研究电磁场对偶离散几何法, 探讨在二维非结构化网格离散空间上相应的寄生电容提取算法, 其中重点考察其对偶特性以及能量互补特性。基于该特性,同时采用对偶的两种方法能够有效地消除网格离散带来的误差,比采用单一方法更快地逼近真实解,从而可发展出静电场能量快速算法。并从理论与实例两方面将其与对偶有限元法实施分析对比。离散几何法采用对偶两套网格上的标量电势作为未知量,具有简单的形式与良好的精度,有望成为相关领域的一种主流方法。     

塑封铜引线集成电路开封方法

在集成电路高速发展的时代,内引线为铜的集成电路因为低廉的价格和性能方面的优势,将越来越多地被制造和改进,破坏性物理分析(DPA)中也将会遇到大量的塑封铜引线集成电路,这类器件开封容易引起铜引线、键合点的腐蚀等问题。对这类器件研究后的开封方法是：激光开封后一定比例的混酸腐蚀能使铜线和键合点完好保留,芯片表面无塑封料残留。本文提供了一种对塑封铜引线集成电路进行开封的可靠方法。     

Operation of integrated InGaAsP-InP optical amplifier-monitoringdetector with feedback control circuit

Monolithic integration of a monitoring detector with an optical amplifier simplifies the use of an amplifier in lightwave systems. The structure and performance are described of a monolithically integrated semiconductor optical amplifier with low-loss Y-branching waveguides and a monitoring p-i-n detector. The photocurrent of the integrated detector can be used as a single control parameter for amplifier output leveling, gain optimization, and in situ monitoring of facet antireflective coatings     

混合集成电路金铝键合退化与控制研究动态

混合集成电路的两种金铝键合系统,有着不完全相同的两种退化模式。综述了相关的退化机理和控制方法的研究状况。金丝与芯片铝膜的Au/Al键合系统,是键合IMC、Kirkendall空洞导致其界面开裂失效;铝丝与厚膜金导体的Al/Au键合系统,除了界面开裂外,还存在键合根部因铝原子向IMC过度迁移而形成铝丝内部空洞导致铝丝断裂。采用铜丝代替金丝,可有效控制Au/Al键合系统的退化;采用过渡垫片或在金浆料中加入少量Pd,同时减少金导体膜厚度,可有效控制铝丝Al/Au键合系统的退化。     

Field acceleration factor for dielectric breakdown of MOS devices

In this paper a model is presented for estimating the field acceleration factor for dielectric breakdown of SiO₂. Using the observation that the total charge through the oxide is invariant (for MOS capacitors fabricated by identical process steps) and assuming that the I-V characteristic is dominated by Fowler Nordheim tunneling prior to breakdown, a simple expression for the acceleration factor can be obtained. The expression gives a good fit to experimentally obtained acceleration factors in the literature. It also indicates that the acceleration factor is field dependent such that the logarithm of acceleration factor vs field is not a straight line and care is required while extrapolating the results of accelerated testing.     

METHOD OF PARAMETER STATISTICAL ANALYSIS FOR BIPOLAR INTEGRATED CIRCUIT DESIGN

The method and procedure of realizing parameter statistical correlation analysis ofbipolar analog IC's are given,and the statistical model of parameter are constructed with doubleparameters(B_F,R_S).Based on the comparison and analysis of the circuit characteristics,it isshown that the method can be used for analysis and design of bipolar IC's.     

加速度传感器信号处理集成电路的研制

设计并制作了一种用于差分电容式加速度传感器的信号处理电路。该电路具有模拟和脉宽调制两种输出方式，能够将差分电容的变化通过模拟电平和输出脉冲信号的占空比表征，实现了对差分电容式加速度传感器信号的测量。电路中集成了自检测驱动单元。电路采用4μmP阱CMOS工艺制作。初步测试结果表明：在1～5pF内，电路的灵敏度为10．7V／pF，可满足大多数差分电容式传感器信号处理的要求。     

加速度传感器信号处理集成电路的研制

设计并制作了一种用于差分电容式加速度传感器的信号处理电路。该电路具有模拟和脉宽调制两种输出方式 ,能够将差分电容的变化通过模拟电平和输出脉冲信号的占空比表征 ,实现了对差分电容式加速度传感器信号的测量。电路中集成了自检测驱动单元。电路采用 4 μmP阱CMOS工艺制作。初步测试结果表明 :在 1～ 5 pF内 ,电路的灵敏度为 10 .7V/ pF ,可满足大多数差分电容式传感器信号处理的要求。     

A capacitive sensing integrated circuit for detection of micromotorcritical angles

The theory, design, and measured performance of an integrated circuit which enables closed-loop control of electrostatic micromotors is presented. The micromotor control integrated circuit (MCIC) consists of low-noise sense electronics designed to detect critical rotor angles to a resolution of 0.5° (0.05 fF) at a 1-MHz sampling rate, and control logic which cycles the micromotor drive state during continuous rotation to maintain maximum torque, independent of loading. Noise due to MOSFET switches and amplifiers in the analog section is modeled and shown to be 32 μV referred to the system input, i.e., about half the desired switching resolution. The MCIC was fabricated using a 2-μm, n-well CMOS process and functions as expected. The noise probability density function was measured using MCIC's digital output for different values of input-to-ground capacitance in order to verify the noise model. Good agreement with theory was observed, although the comparator exhibited some offset and hysteresis