Carbon‐Nanotube‐Confined Vertical Heterostructures with Asymmetric Contacts

Van der Waals (vdW) heterostructures have received intense attention for their efficient stacking methodology with 2D nanomaterials in vertical dimension. However, it is still a challenge to scale down the lateral size of vdW heterostructures to the nanometer and make proper contacts to achieve optimized performances. Here, a carbon‐nanotube‐confined vertical heterostructure (CCVH) is employed to address this challenge, in which 2D semiconductors are asymmetrically sandwiched by an individual metallic single‐walled carbon nanotube (SWCNT) and a metal electrode. By using WSe₂ and MoS₂, the CCVH can be made into p‐type and n‐type field effect transistors with high on/off ratios even when the channel length is 3.3 nm. A complementary inverter was further built with them, indicating their potential in logic circuits with a high integration level. Furthermore, the Fermi level of SWCNTs can be efficiently modulated by the gate voltage, making it competent for both electron and hole injection in the CCVHs. This unique property is shown by the transition of WSe₂ CCVH from unipolar to bipolar, and the transition of WSe₂/MoS₂ from p–n junction to n–n junction under proper source–drain biases and gate voltages. Therefore, the CCVH, as a member of 1D/2D mixed heterostructures, shows great potentials in future nanoelectronics and nano‐optoelectronics.     

Chemically Tuned p‐ and n‐Type WSe2 Monolayers with High Carrier Mobility for Advanced Electronics

Monolayers of transition metal dichalcogenides (TMDCs) have attracted a great interest for post‐silicon electronics and photonics due to their high carrier mobility, tunable bandgap, and atom‐thick 2D structure. With the analogy to conventional silicon electronics, establishing a method to convert TMDC to p‐ and n‐type semiconductors is essential for various device applications, such as complementary metal‐oxide‐semiconductor (CMOS) circuits and photovoltaics. Here, a successful control of the electrical polarity of monolayer WSe₂ is demonstrated by chemical doping. Two different molecules, 4‐nitrobenzenediazonium tetrafluoroborate and diethylenetriamine, are utilized to convert ambipolar WSe₂ field‐effect transistors (FETs) to p‐ and n‐type, respectively. Moreover, the chemically doped WSe₂ show increased effective carrier mobilities of 82 and 25 cm² V^?1s^?1 for holes and electrons, respectively, which are much higher than those of the pristine WSe₂. The doping effects are studied by photoluminescence, Raman, X‐ray photoelectron spectroscopy, and density functional theory. Chemically tuned WSe₂ FETs are integrated into CMOS inverters, exhibiting extremely low power consumption ( ≈ 0.17 nW). Furthermore, a p‐n junction within single WSe₂ grain is realized via spatially controlled chemical doping. The chemical doping method for controlling the transport properties of WSe₂ will contribute to the development of TMDC‐based advanced electronics.     

Printing Semiconductor–Insulator Polymer Bilayers for High‐Performance Coplanar Field‐Effect Transistors

Source–semiconductor–drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next‐generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross‐talk among different devices, and simplify the fabrication process of circuits. Here, a one‐step, drop‐casting‐like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3‐hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO₂ dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor–insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor–insulator bilayer structure is an ideal system for injecting charges into the insulator via gate‐stress, and the thus‐formed PS electret layer acts as a “nonuniform floating gate” to tune the threshold voltage and effective mobility of the transistors. Effective field‐effect mobility higher than 1 cm² V^?1 s^?1 with an on/off ratio > 10⁷ is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits.     

Reconfigurable Diodes Based on Vertical WSe2 Transistors with van der Waals Bonded Contacts

New device concepts can increase the functionality of scaled electronic devices, with reconfigurable diodes allowing the design of more compact logic gates being one of the examples. In recent years, there has been significant interest in creating reconfigurable diodes based on ultrathin transition metal dichalcogenide crystals due to their unique combination of gate‐tunable charge carriers, high mobility, and sizeable band gap. Thanks to their large surface areas, these devices are constructed under planar geometry and the device characteristics are controlled by electrostatic gating through rather complex two independent local gates or ionic‐liquid gating. In this work, similar reconfigurable diode action is demonstrated in a WSe₂ transistor by only utilizing van der Waals bonded graphene and Co/h‐BN contacts. Toward this, first the charge injection efficiencies into WSe₂ by graphene and Co/h‐BN contacts are characterized. While Co/h‐BN contact results in nearly Schottky‐barrier‐free charge injection, graphene/WSe₂ interface has an average barrier height of ≈80 meV. By taking the advantage of the electrostatic transparency of graphene and the different work‐function values of graphene and Co/h‐BN, vertical devices are constructed where different gate‐tunable diode actions are demonstrated. This architecture reveals the opportunities for exploring new device concepts.     

Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area-Efficient Computation

2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area-efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe₂) field-effect transistors (FETs) via introducing hexagonal boron nitride (h-BN) as the interfacial dielectric layer is devised. By modulating the h-BN thickness, the carrier type of WSe₂ FETs has been switched from hole to electron. The ultrathin body of WSe₂, combined with the effective polarity control, together contribute to the versatile single-transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. The unique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.     

Gate‐Controlled BP–WSe2 Heterojunction Diode for Logic Rectifiers and Logic Optoelectronics

p–n junctions play an important role in modern semiconductor electronics and optoelectronics, and field‐effect transistors are often used for logic circuits. Here, gate‐controlled logic rectifiers and logic optoelectronic devices based on stacked black phosphorus (BP) and tungsten diselenide (WSe₂) heterojunctions are reported. The gate‐tunable ambipolar charge carriers in BP and WSe₂ enable a flexible, dynamic, and wide modulation on the heterojunctions as isotype (p–p and n–n) and anisotype (p–n) diodes, which exhibit disparate rectifying and photovoltaic properties. Based on such characteristics, it is demonstrated that BP–WSe₂ heterojunction diodes can be developed for high‐performance logic rectifiers and logic optoelectronic devices. Logic optoelectronic devices can convert a light signal to an electric one by applied gate voltages. This work should be helpful to expand the applications of 2D crystals.     

Spontaneous heteroassembly of 2D semiconducting van der Waals materials in random solution phase

van der Waals heterostructures (vdWHs), consisting of more than one type of atomically thin 2D crystal layers are emerging platforms for interesting electrical, optical, and catalytic applications. High yield production of vdWHs with atomic scale precision is crucial prerequisite for practical utilization. Here we present a generalized approach of random solution phase, high yield heteroassembly of semiconducting vdWHs by exploiting inherent surface charge states of 2D materials as well as chemical affinity of specific ligand end-functionalities. Facile removal of noncovalent functionalized ligands via simple pH reversal enables clean interfaces within vdWHs, yielding outstanding optoelectrical and electrochemical properties driven by fluent interfacial charge transfer among the layered 2D structures. The generality of this procedure is demonstrated by the formation of a series of different vdWHs such as WSe₂-MoS₂, graphene–MoS₂ - and phospherene–WSe₂ heterostructures. Atomically thin WSe₂–MoS₂ phototransistor displayed an exceptionally fast response time with high sensitivity. Graphene–MoS₂ overcomes the inherent charge transfer issue of MoS₂ for electrochemical catalyst. Phospherene–WSe₂ successfully addresses poor ambient stability of phospherene together with enhanced surface activity towards chemical sensing.     

Impact of H‐Doping on n‐Type TMD Channels for Low‐Temperature Band‐Like Transport

Band‐like transport behavior of H‐doped transition metal dichalcogenide (TMD) channels in field effect transistors (FET) is studied by conducting low‐temperature electrical measurements, where MoTe₂, WSe₂, and MoS₂ are chosen for channels. Doped with H atoms through atomic layer deposition, those channels show strong n‐type conduction and their mobility increases without losing on‐state current as the measurement temperature decreases. In contrast, the mobility of unintentionally (naturally) doped TMD FETs always drops at low temperatures whether they are p‐ or n‐type. Density functional theory calculations show that H‐doped MoTe₂, WSe₂, and MoS₂ have Fermi levels above conduction band edge. It is thus concluded that the charge transport behavior in H‐doped TMD channels is metallic showing band‐like transport rather than thermal hopping. These results indicate that H‐doped TMD FETs are practically useful even at low‐temperature ranges.     

Various and Tunable Transport Properties of WSe2 Transistor Formed by Metal Contacts

The abundant electronic and optical properties of 2D materials that are just one‐atom thick pave the way for many novel electronic applications. One important application is to explore the band‐to‐band tunneling in the heterojunction built by different 2D materials. Here, a gate‐controlled WSe₂ transistor is constructed by using different work function metals to form the drain (Pt) and source (Cr) electrodes. The device can be gate‐modulated to exhibit three modes of operation, i.e., the tunneling mode with remarkable negative differential resistance, the transition mode with a second electron tunneling phenomenon for backward bias, and finally the conventional diode mode with rectifying characteristics. In contrast to the heterojunctions built by different 2D materials, these devices show significantly enhanced tunneling current by two orders of magnitude, which may largely benefit from the clean interfaces. These results pave the way toward design of novel electronic devices using the modulation of metal work functions.     

Synthesis of 2D Layered BiI3 Nanoplates,BiI3/WSe2van der Waals Heterostructures and Their Electronic,Optoelectronic Properties

Two–dimensional layered materials (2DLMs) have attracted considerable recent interest as a new material platform for fundamental materials science and potential new technologies. Here we report the growth of layered metal halide materials and their optoelectronic properties. BiI₃ nanoplates can be readily grown on SiO₂/Si substrates with a hexagonal geometry, with a thickness in the range of 10–120 nm and a lateral dimension of 3–10 µm. Transmission electron microscopy and electron diffraction studies demonstrate that the individual nanoplates are high quality single crystals. Micro‐Raman studies show characteristic A _g band at ≈115 cm^?1 with slight red‐shift with decreasing thickness, and micro‐photoluminescence studies show uniform emission around 690 nm with blue‐shift with decreasing thickness. Electrical transport studies of individual nanoplates show n‐type semiconductor characteristics with clear photoresponse. Further, the BiI₃ can be readily grown on other 2DLMs (e.g., WSe₂) to form van der Waals heterostructures. Electrical transport measurements of BiI₃/WSe₂ vertical heterojunctions demonstrate p–n diode characteristics with gate‐tunable rectification behavior and distinct photovoltaic effect. The synthesis of the BiI₃ nanoplates can expand the library of 2DLMs and enable a wider range of van der Waals heterostructures.     

Vertical ZnO Nanotube Transistor on a Graphene Film for Flexible Inorganic Electronics

The bottom‐up integration of a 1D–2D hybrid semiconductor nanostructure into a vertical field‐effect transistor (VFET) for use in flexible inorganic electronics is reported. Zinc oxide (ZnO) nanotubes on graphene film is used as an example. The VFET is fabricated by growing position‐ and dimension‐controlled single crystal ZnO nanotubes vertically on a large graphene film. The graphene film, which acts as the substrate, provides a bottom electrical contact to the nanotubes. Due to the high quality of the single crystal ZnO nanotubes and the unique 1D device structure, the fabricated VFET exhibits excellent electrical characteristics. For example, it has a small subthreshold swing of 110 mV dec^?1, a high I_max/I_min ratio of 10⁶, and a transconductance of 170 nS µm^?1. The electrical characteristics of the nanotube VFETs are validated using 3D transport simulations. Furthermore, the nanotube VFETs fabricated on graphene films can be easily transferred onto flexible plastic substrates. The resulting components are reliable, exhibit high performance, and do not degrade significantly during testing.     

High-performance multilayer WSe2 p-type field effect transistors with Pd contacts for circuit applications

WSe₂ is thought to be one of the best emerging p-type transition metal dichalcogenide (TMD) materials for potential low-power complementary metal oxide semiconductor (CMOS) circuit applications. However, the contact barrier and the interface quality hinder the performance of p-type field effect transistors (FETs) with WSe₂ films. In this work, metals with different work functions—Pd, Pt, and Ag—were systematically investigated as contacts for WSe₂ to decrease the contact resistances at source/drain electrodes and potentially improve transistor performance. Optimized p-type multilayer WSe₂ FETs with Pd contacts were successfully fabricated, and excellent electrical characteristics were obtained: a hole mobility of 36 cm²V^?1 s^?1; a high on/off ratio, over 10⁶; and a record low sub-threshold swing, SS?=?95 mV/dec, which may be attributed to the small Schottky barrier height of 295 meV between Pd and WSe₂, and strong Fermi-level pinning near the top of the valence band at the interface. Finally, a full-functional CMOS inverter was also demonstrated, consisting of a p-type WSe₂ FET together with a normal n-type MoS₂ FET. This confirmed the potential of TMD FETs in future low-power CMOS digital circuit applications.

     

WSe2 Homojunction Devices: Electrostatically Configurable as Diodes,MOSFETs, and Tunnel FETs for Reconfigurable Computing

In this paper, electrostatically configurable 2D tungsten diselenide (WSe₂) electronic devices are demonstrated. Utilizing a novel triple‐gate design, a WSe₂ device is able to operate as a tunneling field‐effect transistor (TFET), a metal–oxide–semiconductor field‐effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band‐to‐band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self‐consistent full‐band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub‐60 mV dec^?1 SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low‐power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.     

High-performance multilayer WSe<Subscript>2</Subscript> field-effect transistors with carrier type control

In this study, high-performance multilayer WSe₂ field-effect transistor (FET) devices with carrier type control are demonstrated via thickness modulation and a remote oxygen plasma surface treatment. Carrier type control in multilayer WSe₂ FET devices with Cr/Au contacts is initially demonstrated by modulating the WSe₂ thickness. The carrier type evolves with increasing WSe₂ channel thickness, being p-type, ambipolar, and n-type at thicknesses <3, ～4, and >5 nm, respectively. The thickness-dependent carrier type is attributed to changes in the bandgap of WSe₂ as a function of the thickness and the carrier band offsets relative to the metal contacts. Furthermore, we present a strong hole carrier doping effect via remote oxygen plasma treatment. It non-degenerately converts n-type characteristics into p-type and enhances field-effect hole mobility by three orders of magnitude. This work demonstrates progress towards the realization of high-performance multilayer WSe₂ FETs with carrier type control, potentially extendable to other transition metal dichalcogenides, for future electronic and optoelectronic applications.

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Eliminating Overerase Behavior by Designing Energy Band in High‐Speed Charge‐Trap Memory Based on WSe2

Atomic crystal charge trap memory, as a new concept of nonvolatile memory, possesses an atomic level flatness interface, which makes them promising candidates for replacing conventional FLASH memory in the future. Here, a 2D material WSe₂ and a 3D Al₂O₃/HfO₂/Al₂O₃ charge‐trap stack are combined to form a charge‐trap memory device with a separation of control gate and memory stack. In this device, the charges are erased/written by built‐in electric field, which significantly enhances the write speed to 1 µs. More importantly, owing to the elaborate design of the energy band structure, the memory only captures electrons with a large electron memory window over 20 V and trap selectivity about 13, both of them are the state‐of‐the‐art values ever reported in FLASH memory based on 2D materials. Therefore, it is demonstrated that high‐performance charge trap memory based on WSe₂ without the fatal overerase issue in conventional FLASH memory can be realized to practical application.     

Van der Waals Integration of Bismuth Quantum Dots–Decorated Tellurium Nanotubes (Te@Bi) Heterojunctions and Plasma‐Enhanced Optoelectronic Applications

Van der Waals (vdW)‐integrated heterojunctions have been widely investigated in optoelectronics due to their superior photoelectric conversion capability. In this work, 0D bismuth quantum dots (Bi QDs)‐decorated 1D tellurium nanotubes (Te NTs) vdW heterojunctions (Te@Bi vdWHs) are constructed by a facile bottom‐up assembly process. Transient absorption spectroscopy suggests that Te@Bi vdWH is a promising candidate for new‐generation optoelectronic devices with fast response properties. The subsequent experiments and density functional theory calculations demonstrate the vdW interaction between Te NTs and Bi QDs, as well as the enhanced optoelectronic characteristics owing to the plasma effects at the interface between Te NTs and Bi QDs. Moreover, Te@Bi vdWHs‐based photodetectors show significantly improved photoresponse behavior in the ultraviolet region compared to pristine Te NTs or Bi QDs‐based photodetectors. The proposed integration of vdWHs is expected to pave the way for constructing new nanoscale heterodevices.     

Tunable SnSe2/WSe2 Heterostructure Tunneling Field Effect Transistor

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band‐edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe₂/WSe₂ van der Waals heterostructures with SnSe₂ as the p‐layer and WSe₂ as the n‐layer. The energy band alignment changes from a staggered gap band offset (type‐II) to a broken gap (type‐III) when changing the negative back‐gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~10⁴) or an n‐type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec^?1 for exceeding two decades of drain current with a minimum of 37 mV dec^?1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The I _ON/I _OFF ratio of the transfer characteristics is >10⁶, accompanying a high ON current >10^?5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low‐power consumption devices.     

Gate‐Tunable Graphene–WSe2 Heterojunctions at the Schottky–Mott Limit

Metal–semiconductor interfaces, known as Schottky junctions, have long been hindered by defects and impurities. Such imperfections dominate the electrical characteristics of the junction by pinning the metal Fermi energy. Here, a graphene–WSe₂ p‐type Schottky junction, which exhibits a lack of Fermi level pinning, is studied. The Schottky junction displays near‐ideal diode characteristics with large gate tunability and small leakage currents. Using a gate electrostatically coupled to the WSe₂ channel to tune the Schottky barrier height, the Schottky–Mott limit is probed in a single device. As a special manifestation of the tunable Schottky barrier, a diode with a dynamically controlled ideality factor is demonstrated.     

Magnetic‐Induced‐Piezopotential Gated MoS2 Field‐Effect Transistor at Room Temperature

Utilizing magnetic field directly modulating/turning the charge carrier transport behavior of field‐effect transistor (FET) at ambient conditions is an enormous challenge in the field of micro–nanoelectronics. Here, a new type of magnetic‐induced‐piezopotential gated field‐effect‐transistor (MIPG‐FET) base on laminate composites is proposed, which consists of Terfenol‐D, a ferroelectric single crystal (PMNPT), and MoS₂ flake. When applying an external magnetic field to the MIPG‐FET, the piezopotential of PMNPT triggered by magnetostriction of the Terfenol‐D can serve as the gate voltage to effectively modulate/control the carrier transport process and the corresponding drain current at room temperature. Considering the two polarization states of PMNPT, the drain current is diminished from 9.56 to 2.9 µA in the P_up state under a magnetic field of 33 mT, and increases from 1.41 to 4.93 µA in the P_down state under a magnetic field of 42 mT and at a drain voltage of 3 V. The current on/off ratios in these states are 330% and 432%, respectively. This work provides a novel noncontact coupling method among magnetism, piezoelectricity, and semiconductor properties, which may have extremely important applications in magnetic sensors, memory and logic devices, micro‐electromechanical systems, and human–machine interfacing.     

Device degradation behavior and polysilicon film morphology of thin film transistors fabricated using advanced excimer laser lateral solidification techniques

The degradation of polysilicon thin film transistors fabricated in films obtained using variations of advanced through-mask excimer laser anneal sequential lateral solidification (SLS) schemes was investigated. The morphology and grain structure of these 50 nm thick polysilicon films was studied using SEM and AFM. Very elongated or square-like polycrystalline silicon grains were observed, as shaped by each crystallization technique. Hot carrier stressing measurements, under gate and drain DC biases, were performed and the TFT device parameters and characteristics were extracted for various stressing times. The threshold voltage V_th, subthreshold slope S and transconductance G_m were observed to exhibit shifts with stressing time, indicating some active layer and interface degradation ascribed to hot carrier injection and trap generation. These shifts depended both on stress conditions and on the fabrication technique used. The hot carrier stressing results thus indicate that the material structure affects the degradation rates of the TFT parameters and trap densities. Furthermore, the device structure and the crystallization conditions, with the resulting film morphology, affect not only the TFT degradation behavior but also other aspects of device performance; the susceptibility to drain current avalanche effects was found to be lower for TFTs in 2^N-shot polysilicon compared to ones in very elongated grain (directional) material.