Generation-recombination transient effects in partially depletedSOI transistors: systematic experiments and simulations

A synthesis of the most frequent transient phenomena due to floating-body effects in partially depleted SOI MOSFET's is presented. The dominant physical mechanisms are examined through a variety of experiments. Comprehensive models which predict the transient effects are included in SOISPICE. Simulated transients involving both generation and recombination are fully validated by the experiments and are shown to he useful for reliable carrier lifetime extraction as well as SOI circuit simulation     

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L_eff below 0.2 μm     

Physical subthreshold MOSFET modeling applied to viable design ofdeep-submicrometer fully depleted SOI low-voltage CMOS technology

An insightful study of the subthreshold characteristics of deep-submicrometer fully depleted SOI MOSFET's, based on two-dimensional numerical (PISCES) device simulations, shows that the gate swing and off-state current are governed by gate bias-dependent source/drain charge sharing, which controls back-channel as well as front-channel conduction. The insight from this study guides the development of a physical, two-dimensional analytic model for the subthreshold current and charge, which is linked to our strong-inversion formalism in SOISPICE for circuit simulation. The model is verified by PISCES simulations of scaled devices. The utility of the model in SOISPICE is demonstrated by using it to define a viable design for deep-submicrometer fully depleted SOI CMOS technology based on simulated speed and static power in low-voltage digital circuits     

SOI MOSFET自加热效应测试方法

为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。     

A physical charge-based model for non-fully depleted SOI MOSFET'sand its use in assessing floating-body effects in SOI CMOS circuits

A new model for the non-fully depleted (NFD) SOI MOSFET is developed and used to study floating-body effects in SOI CMOS circuits. The charge-based model is physical, yet compact and thus suitable for device/circuit simulation. Verified by numerical device simulations and test-device measurements, and implemented in (SOI)SPICE, it reliably predicts floating-body effects resulting from free-carrier charging in the NFD/SOI MOSFET, including the purportedly beneficial supra-ideal sub-threshold slope due to impact ionization and a saturation current enhancement due to thermal generation. SOISPICE CMOS circuit simulations reveal that the former effect is not beneficial and could be detrimental, but the latter effect can be beneficial, especially in low-voltage applications, when accompanied by a dynamic floating-body effect that effectively reduces static power. The dynamic floating-body effects are hysteretic, however, and hence exploitation of the beneficial ones will necessitate device/circuit design scrutiny aided by physical models such as the one presented herein     

Thermal and package performance limitations in LDMOSFET's for RFICapplications

This paper presents a systematic study of the limitations imposed by thermal and packaging considerations on radio-frequency (RF) performance of Si bulk and silicon-on-insulator (SOI) lateral DMOSFET's (LDMOSFET's). Several bulk and SOI devices are studied with the help of measurements as well as two-dimensional device simulations incorporating electrothermal models. Model parameters are extracted and used in circuit simulators to perform RF characterization of these devices. Further, a new three-region theory for the LDMOSFET is discussed and used to evaluate the static and RF performance of the devices in a nonisothermal environment. This paper shows that the package plays an important role in RF performance of SOI and bulk devices due to self-heating effects within the device. A detailed DC and RF performance evaluation is presented. Significant drift is observed in RF performance of bulk and SOI devices due to self-heating considerations. The physical understanding of these thermal effects within the device can facilitate the design of better packages for bulk and SOI devices     

A comparative analysis of the dynamic behavior of BTG/SOI MOSFETsand circuits with distributed body resistance

To examine the dynamic nature of body-tied-to-gate (BTG) partially depleted SOI MOSFETs, CMOS inverter circuits (nine-stage ring oscillators and 50-stage chains) are simulated with SOISPICE, accounting for the BTG distributed body resistance. Due to the physical nature of the UFSOI model in SOISPICE, both the static and dynamic characteristics of the BTG device, contrasted to floating-body (FB) and body-tied-to-source (BTS) SOI MOSFETs, are faithfully revealed. Results give insight on previously measured, yet inadequately explained, dynamic behavior of the BTG device. Further, problematic hysteretic behavior associated with the dynamic operation of the device with realistic body sheet resistance is described, suggesting design constraints on the maximum device width. Finally, a performance assessment of the BTG device configuration in ultra-low-power CMOS digital applications is offered and compared with FB and BTS, indicating that the optimal configuration is in fact application-specific     

Fabrication and Simulation of Silicon-on-Insulator Structure with Si3N4 as a Buried Insulator

In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3N4 film as a buried insulator (SOSN) are successfully formed using epitaxial layer transfer technology for the first time.The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile.Experiment results show that the buried Si3N4 layer is amorphous and the new SOI material has good structural and electrical properties.The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs.Furthermore,the channel temperature and negative differential resistance are reduced during high-temperature operation,suggesting that SOSN can effectively mitigate the self-heating penalty.The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.     

Compact Modeling Methodology of Strained-Si Channel-on-Insulator (SSOI) MOSFETs

Compact physical models for SSOI MOSFETs are presented. The models consider specific features for strained-Si devices including SSOI such as mobility enhancement, band offsets, junction capacitance, and self-heating effects. All of the floating-body current components in conventional SOI structure, which are generation/recombination current, reverse-bias (band-to-band and trap-assisted) junction tunneling currents, gate-induced drain leakage current, gatebody oxide tunneling current, and impact ionization current are applied to the SSOI device, and their effects are discussed. The model validity is confirmed by fabricated 70?nm bulk-Si (control) and strained-Si devices.     

Off-state modulation of SOI floating-body

Off-state modulation of the floating-body potential in partially depleted silicon-on-insulator (PDSOI) transistors from the 90-nm technology generation is observed using pulsed current-voltage (I-V) measurements. Varying the off-value of the gate voltage is shown to either decrease the transient on-current (I/sub on,trans/) of PDSOI devices through gate-to-body leakage or increase I/sub on,trans/ due to gate-induced drain leakage. Dependence of I/sub on,trans/ on off-state gate bias is not observed in bulk devices, PDSOI devices with body contacts, or fully depleted SOI devices, confirming the role of floating-body in the observed effects. Thus, off-state conditions should be accounted for when considering floating-body effects and when using pulsed I-V measurements to study self-heating.     

Impact of device physics on DG and SOI MOSFET linearity

The influence of different physical mechanisms on MOSFET linearity is analyzed using 2D TCAD device simulations. In particular, the RF linearity performance of 50 nm gate length SOI and DG-MOSFETs are investigated and compared with traditional bulk MOSFETs. We employ the hydrodynamic (HD) transport model to account for non-equilibrium carrier dynamics and the density gradient approximation for quantum mechanical effects. Impact ionization of channel carriers and self-heating effect (SHE) are also accounted for in the thin-body devices. Our results disclose the relationship between various aspects of device physics and linearity. We show that linearity performance is particularly sensitive to non-local effects and are lowered due to SHE. Quantum mechanical effects appear to have a small positive impact on linearity. Drift-diffusion approximation is found to be unreliable for linearity analysis of DG MOSFETs due to large overestimation from this model. We also observe that linearity has an anomalous monotonous dependence on the ambient temperature.     

Temperature dependence of threshold voltage in thin-film SOIMOSFETs

A first-order model for the temperature dependence of threshold voltage in thin-film silicon-on-insulator (SOI) n-MOSFETs is described. The temperature dependence of the threshold voltage of thin-film SOI n-channel MOSFETs is analyzed. Threshold voltage variation with temperature is significantly smaller in thin-film (fully depleted) devices than in thick-film SOI and bulk devices. The threshold voltage is shown to be dependent on the depletion level of the device, i.e. whether it is fully depleted or not. There exists a critical temperature below which the device is fully depleted, and above which the device operates in the thick-film regime     

B-Spline Based, Large-Signal DC and Microwave-Model for SOI MOSFETs

We present a large/small-signal, non-quasi-static, charge conserving, SOI MOSFET modeling technique suitable for DC and high frequency circuit design. The device model is extracted from small signal microwave iso-thermal Y-parameter data and DC I–V characteristics. Low frequency dispersions associated with self-heating and floating body effects are verified to not limit the performance of this technique since it relies on both DC and transient I–V characteristics. The technique is applied to the modeling of a short-channel, partially depleted, SOI nMOSFET simulated on PISCES. The model generated is incorporated into a circuit simulator, which is used to perform large-signal transient and harmonic balance simulations. The transient I–V and gate charge extracted from the iso-thermal small-signal microwave Y-parameters, are in excellent agreement with the iso-thermal transient I–V and gate charge obtained from PISCES, respectively. The model topology is extended with a parasitic bipolar sub-circuit which automatically calculates the DC operating point for self-biasing circuits. Transient and non-linear power characterization results predicted with this model agree well with those obtained from PISCES for a wide range of input power drives. A complete electro-thermal model is proposed and verified to be able to predict temperature and transient I–V response.     

以Si3N4为埋层的SOI结构制备与器件模拟

为了减少经典SOI器件的自加热效应,首次成功地用外延方法制备以Si3N4薄膜为埋层的新结构SOSN,用HRTEM和SRP表征了SOI的新结构.实验结果显示,Si3N4层为非晶状态,新结构的SOSN具有良好的结构和电学性能.对传统SOI和新结构SOI的MOSFETs输出电流的输出特性和温度分布用TCAD仿真软件进行了模拟.模拟结果表明,新结构SOSN的MOSFET器件沟道温度和NDR效益都得到很大的降低,表明SOSN能够有效地克服自加热效应和提高MOSFET漏电流.     

Analysis of floating body induced transient behaviors in partiallydepleted thin film SOI devices

Emphasis toward manufacturability of thin film SOI devices has prompted more attention on partially depleted devices. In this paper, drain current transients in partially depleted SOI devices due to floating-body effects are investigated quantitatively. A one-dimensional analytical model is developed to predict the transient effect and MEDICI simulation is performed to confirm the model. With the model, the amount of the turn-on current enhancement and the turn-off current suppression are calculated. The transient characteristics can be used in investigating the quality of the SOI materials by determining the carrier lifetime. The impact of the transient effect on the device parameter extraction is described     

Temperature dependence of hot-carrier-induced degradation in 0.1μm SOI nMOSFETs with thin oxide

This letter investigates hot-carrier-induced degradation on 0.1 μm partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect     

SOI技术问题和BSIM3SOIv1.3模型参数特点

SOI器件具有高速、低压、低功耗、抗辐照、耐高温等体硅器件不具备的优点,SOI CMOS技术开始用于深亚微米高速、低功耗、低电压大规模集成电路应用。但SOI技术还面临浮体效应、自加热效应等问题的挑战。作为SOI模型国际标准,BSIM3SOIv1.3提出了新的模型参数解决方案。BSIMPDSPICE器件模型是基于物理意义的模型,是在体硅MOS器件模型工业标准(BSIM3V3)的基础上开发而成,BSIMPD针对SOI固有的浮体效应引起的动态特性,自加热和体接触提出相应的模型参数。     

Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs

Self-heating in silicon-on-insulator (SOI) MOSFETs has become one of the vital issues for design, characterization, optimization and reliability prediction of SOI devices and integrated circuits due to the low thermal conductive buried oxide (BOX) and the continual increase in the microelectronic packaging density. Thermal models that are accurate and detailed enough to provide device temperature profiles and efficient enough for large scale electro-thermal simulation are therefore strongly desirable. This paper discusses the fundamental concepts for modeling of heat flow in semiconductor devices. A brief overview for the conventional approaches to thermal modeling of the SOI devices is given. Improved steady-state and dynamic SOI heat flow models based on the SOI film thermal resistance for efficient prediction of steady-state and dynamic temperature variations in SOI devices are presented. These improved models are applied to investigate temperature distributions and temporal evolution of the junction temperature in SOI nMOSFETs.     

Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.     

Substrate engineering for improved transient breakdown voltage in SOI lateral power MOS

An innovative design concept for the silicon-on-insulator (SOI) lateral power devices that can be applied to a wide class of high-voltage applications, in particular those employing resonant switching, is presented. A nonuniformly doped substrate is used to improve the transient breakdown performance of the lateral MOSTs. The simulation results show that the proposed device exhibits a largely improved transient breakdown. That is, for a time interval that ranges from 10 /spl mu/s to 10 ms depending on the silicon characteristics and temperature, the device exhibits a blocking voltage that is almost double when compared to the static blocking voltage. By using the novel concept presented here, one can design a high-performance device with a high transient breakdown, which is needed for most switching applications. The device will benefit from a smaller substrate oxide thickness designed for a lower static breakdown, which results in reduced self-heating and allows full compatibility with the mainstream SOI material.