大尺寸LTCC 基板高钎透率焊接工艺研究

低温共烧多层陶瓷（Low Temperature Co-fired Ceramic, LTCC）技术在军工电子领域的应用越来越广泛,但是大尺寸多腔体LTCC 基板的钎透率一直是制约LTCC 基板应用范围进一步扩展的重要因素。文中研究了基板可焊性、平面度以及回流焊接工艺等因素对LTCC 基板钎透率的影响规律,并在此基础上完善了大尺寸多腔体LTCC 基板的回流焊接工艺。基板与壳体焊接一次成形,有效控制了焊料流淌;基板钎透率达到95% 以上,避免了对焊缝和多余焊锡的返工返修工作。这些都推动了大尺寸多腔体LTCC 基板在微波组件中的批量应用。     

基于超声热压工艺的三维集成垂直互联技术

三维集成垂直互联技术是实现电子信息系统小型化、轻量化、高密度集成的关键技术,文中将金凸点超声热压技术应用到三维集成多层转接板堆叠工艺中,采用自动侧向剪裁工艺和预整平工艺制备一致性极高的金球微凸点阵列,通过设置合理的超声振幅、压力和温度参数,并优化匹配超声曲线和压力曲线的作用时序,实现硅转接板自底向上高精度、高可靠堆叠,解决超声热压焊接易发生对位焊接偏差、焊点滑移的问题.基于金凸点超声热压技术的三维集成垂直互联技术拥有低温互联、高温使用的优势,避免了多层堆叠时复杂的温度梯度考虑,并可应对多种类型的焊盘体系,无需制备专用凸点下金属(UBM)层,在三维集成系统级封装技术中具有广阔的应用前景.     

基于混合微电路工艺的多芯片集成双轴磁传感器模块

采用混合微电路工艺,设计了一种基于陶瓷互连基板及封装的多芯片集成(MCM-C)模块,将全固态双轴磁阻传感器及信号处理芯片等集成为微型化、高可靠的传感器模块。模块分别以16位串行数字量输出Y、Z向磁场检测结果,可以直接与各类微处理器接口进行实时数据交换。     

基于田口方法的混合集成基板CMP工艺优化研究

为了提高多芯片组件(Multi-Chip Module,MCM-C/D)技术中低温共烧陶瓷(Low Temperature Co-fired Ceramic,LTCC)基板的表面质量,需要采用化学机械抛光(Chemical Mechanical Polishing,CMP)工艺使基板表面平坦化.文中探讨了基于田口试验方...     

表面安装的电子组件设计与研制

表面安装技术是实现高密度电子组装的卓有成效的途径之一。本文介绍了采用这一技术研制的并已应用于某卫星地面站及机载电子设备的几种电子组件的设计和制造过程。组件几种结构是:以印制板为基板的混合表面安装组件、单层陶瓷基板混合电路组件、集成电路芯片直接安装在多层厚膜陶瓷基板上采用线焊法的混合电路组件。各种组件采用新型元件和新的制造工艺,分析了各种组件的结构特点及实际应用效果。     

LCP 基板制作工艺及其在微波无源电路中的应用

液晶聚合物（LCP）基板是继低温共烧陶瓷（LTCC）后的新一代微波毫米波基板材料,具有损耗小、成本低、使用频率范围大、强度高、重量轻等许多独特的优点。文中详细介绍了LCP制作工艺,对基于LCP基板的微波平面传输线的性能进行了分析,并设计出两层基板的X波段21dB耦合器,为基于LCP多层基板的微波无源电路研制打下基础。     

基于氮化铝HTCC基板的化学镀镍硼工艺研究

氮化铝(AlN)高温共烧陶瓷(High Temperature Co-fired Ceramic,HTCC)基板具有高的热导率以及与芯片匹配的热膨胀系数,是高功率多芯片组件首选的基板材料和封装材料。为了满足封装要求的良好钎焊性能,文中采用化学镀工艺在氮化铝HTCC基板钨导体表面沉积了化学镍钯金镀层。文中对化学镀镍溶液体系和高温热处理的工艺条件进行了研究,对化学镍层的厚度进行了优化。结果表明,高温热处理促使薄镍层向基板表面钨导体扩散,进而提高化学镀层与基底之间的附着力,镀层附着力良好,满足金丝键合和锡铅焊的要求,为微波高功率组件的研制提供了技术支撑。     

一种基于AlN多层HTCC基板的SiP模块封装设计

为了满足工作频带宽、传输速率高、功耗大、集成度高的要求,开展一种基于AlN多层高温共烧陶瓷（High Temperature Co-fired Ceramic, HTCC）基板的系统级封装（System in Package, SiP）模块封装设计研究。通过设计制作AlN多层HTCC基板、SiP模块封装结构电性能仿真、模块安装结构热力学仿真设计、组装工艺优化等系列研究工作研制出了小型化、轻量化、高集成的SiP模块。环境试验结果表明该模块具有良好的可靠性。该研究结果可为小型化、轻量化、高集成的SiP模块设计研发提供借鉴。     

微波基板表面可焊性镀层的制备及性能评估

文中针对低温共烧陶瓷（Low Temperature Co-fired Ceramic, LTCC）微波多层基板高密度布线和多深腔的结构形态,结合化学镀工艺过程及原理,讨论了采用化学镀在LTCC微波多层基板表面制备可焊性镀层的工艺难点。针对某微波多层基板化学镀生产中出现的漏镀和渗镀缺陷,深入分析了各影响因素及作用机理,借助扫描电子显微镜（Scanning Electron Microscope, SEM）、能谱仪（Energy Dispersive Spectrometer, EDS）等微观分析手段,确定了引起漏镀和渗镀缺陷的主要原因,采取酸漂洗、增强玻璃刻蚀条件等措施,解决了漏镀和渗镀的难题。对可焊性镀层的附着力和键合可靠性进行了测试评价,结果表明,金属浆料及可焊性镀层均附着良好,键合强度较高,键合点可靠,能很好地满足微波组件的应用要求。     

热超声倒装键合振动传递与键合强度形成研究

采用多普勒激光振动测量系统，获得了热超声倒装键合过程中工具末端及芯片的振动速度曲线。通过比较分析两条曲线，揭示了热超声倒装键合强度的生成过程：在键合初始阶段，键合界面的相对运动主要发生在芯片金凸点与基板焊盘表面之间，并使其接触表面氧化层和污染层被破坏，裸露出新鲜原子，为金凸点与焊盘间的原子扩散并最终形成键合强度提供条件；随着键合的进行，芯片振动速度开始下降，而工具末端振动速度继续增大（即出现速度分离现象），工具末端和芯片间产生明显相对运动，表明键合强度已产生，芯片金凸点／基板焊盘间的结合力超过工具末端／芯片间的摩擦力；速度分离后芯片与工具末端的振动速度和位移曲线表明了超声振动能量部分耗散在芯片／工具的摩擦上。     

倒装芯片钉头凸点工艺技术

采用钉头凸点工艺进行了倒装芯片上凸点的制备,运用田口试验方法进行设计和试验验证,确定了钉头凸点制备的优化的工艺参数组合。研究结果表明：凸点质量的影响因素依次是超声时间、超声功率和焊接压力,优化的工艺参数组合为超声时间50ms、超声功率0．36w、焊接压力55玎。采用优化后的工艺参数进行凸点制备,获得了稳定性良好的钉头凸点,可满足小批量混合集成微波电路芯片倒装焊接的需要。     

Burr formation during micro via-hole punching process of ceramic and PET double layer sheet

Nowadays, recent electronic equipments are becoming smaller, multi-functional, and more complex. Similarly, low temperature co-fired ceramic (LTCC) has been emerged as a promising technology in the packaging industry. It consists of a multi-layer ceramic sheet, and a three-dimensional circuit. The via hole formation in LTCC plays an important role in providing an electric path for the interconnection between circuits. Therefore, via hole quality has a very important role for ensuring the performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic (before sintering) layer and PET (Polyethylene terephthalate) layer. In this paper, we will discuss about the correlation between hole quality and process condition such as ceramic thickness, tool size, etc. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one will also be discussed.     

Detection of solder bump defects on a flip chip using vibration analysis

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.     

Method of reducing the gap between chips in mosaic photodetector modules

A method is proposed to shape the edges of chips in order to reduce the gap between chips in infrared-sensitive mosaic photodetectors modules. The method involves laser scribing of asymmetric grooves, splitting-off of the edge of the chip surface going under the chip, and the subsequent vertical alignment of the edges using laser radiation. The width of the gap between chips is 1–3 μm.     

A hybrid defect detection for in-tray semiconductor chip

The requirements for high-speed and high-precision defect inspection in semiconductor chip are growing rapidly because of the complicated surface in semiconductor chip. Due to manufacturing tolerance of IC tray, the misalignment from the chip positioning shift and rotation are always presented for the application of in-tray inspection. In the beginning, this paper focuses on compensating the positioning shift and rotation of in-tray chip by using the proposed image alignment algorithm before the defect detection. After applying the process of image alignment, a hybrid approach of defect detection is applied to detect the defects of in-tray chip. Furthermore, this hybrid approach simultaneously detects the defects based on its surface by the following two categories: (1) the complicated surface in the circuit and (2) the primitive surface on the bump. As mentioned above, the image alignment strategy and the adaptive image difference method are applied in the detection of complicated surface, and the design-rule strategy is adapted to detect the defects on bumps. Finally, the experimental results show that the proposed image alignment strategy and hybrid approach can accurately and rapidly inspect the defects of in-tray chip. This approach is superior to the traditional template matching in defect detection. In addition, the computational complexity can be efficiently reduced by the proposed hybrid strategy.     

氮化铝多层共烧陶瓷基板的化学镀镍钯金技术

氮化铝多层高温共烧陶瓷(HTCC)基板具有优良的散热性能和与芯片匹配的热膨胀系数,其热导率比LTCC高两个数量级左右。在HTCC制作过程中,需要使用高熔点的钨浆料,而钨本身不具有可焊性和可键合性,必须对HTCC表面的钨导体进行表面改性,使其具有可焊性和可键合性,便于电子装配。化学镀镍钯金是这种表面改性最理想的方案。在HTCC表面进行化镀的相关文献较少,文中论述了在HTCC上沉积化学镍钯金镀层的原理,探讨了导致化学镍钯金沉积过程中出现的附着力问题的原因,为HTCC上化学镍钯金镀层的质量控制提供了方向指引。     

微电阻焊及其在雷达T/R组件互连中的应用

微电阻焊技术成熟且操作简便,被广泛应用于电子及机械制造领域。文中将其创新性地应用到了雷达T/R组件微波模块的内部互连中。文中首先分析了微波组件中电阻焊的实现工艺与方法,然后应用该技术分别实现了T/R组件的低频连接器与基板之间、射频电路模块之间以及高频连接器接头内部电路的互连。利用该工艺技术方法,可以突破常规引线键合时焊接面可焊性要求较高的限制,可以实现高频、射频电路中金属丝、带（如镀金铜丝、金带、镀金铜箔）的互连。初步验证表明,其焊接质量良好。     

Water-jet-assisted diamond disk dressing characteristics of CMP polishing pad

This paper presents an experimental investigation of the dressing characteristics of a porous polishing pad using a combination of water-jet dressing (WJC) and traditional diamond disk dressing (DDC). The WJC and DDC dressing mechanisms were integrated in order to improve the dressing efficiency. The pad recovery test was performed. In this test, the real-time friction force was determined, scanning electron microscope images were obtained, and the dressed surface topography after prolonged operation without conditioning was examined. The pad cut rate and the rate of removal of the copper substrate by the polishing process were investigated by comparing the results of the WJC?+?DDC, only DDC, and only WJC methods. The experimental results showed that although the WJC can remove the slurry residue from the pad surface and consumes less pad material, it cannot remove the glazed layer formed as a result of plastic deformation, which contributes to the low material removal rate. On the other hand, DDC can remove the glazed layer of the pad and restore the pad asperities; however, a few residual chips still remain on the sides of the pores or inside the pores. WJC?+?DDC cannot only remove the embedded slurry particulates and the glazed layer, but also remove the slurry residue accumulated on the pad surface and restore the pad asperities. In addition, the chip residues in the pores, created by the diamond grit, are completely removed by the WJC?+?DDC conditioning process; the removal of the chip residue helps in obtaining the highest material removal rate. In summary, WJC?+?DDC can be used as an effective pad conditioning method.