Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Application of the floating-gate technique to the study of then-MOSFET gate current evolution due to hot-carrier aging

The evolution of the gate current-voltage (I_g- V_gs) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (V_ds ) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the I_g-V_gs curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is representative of the V_gs=V_ds case. It is demonstrated that electron traps are created in the oxide by both hot-hole and hot-electron injection stresses. They are not present in the devices before aging. They can be easily charged and discharged by short electron and hole injections, respectively     

Dependence of ionization current on gate bias in GaAs MESFETs

The nonmonotonic behavior of gate current I_g as a function of gate-to-source voltage V_gs is reported for depletion-mode double-implant GaAs MESFETs. Experiments and numerical simulations show that the main contribution to I_g (in the range of drain biases studied) comes from impact-ionization-generated holes collected at the gate electrode, and that the bell shape of the I_g(V_gs) curve is strongly related to the drop of the electric field in the channel of the device as V_gs is moved towards positive values     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

Collector-assisted operation of micromachined field-emitter triodes

The field at the tip of a field emitter triode can be expressed by E=βV_g+_γV _c, where V_g and V_c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, _γV_c<<βV _g. The-device is operated in the gate-induced field emission mode and the corresponding I-V_c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I-V_c and transconductance g_m-V_g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly     

A physical model for the gate current injection in p-channelMOSFET's

A quantitative physical model for calculating the hot-electron injection probability, I_G/I_SUB, for both buried and surface p-channel MOSFETs is presented. The model utilizes the two-dimensional potential contours generated by PISCES, and integrates the probability of substrate hot-electron injection across the high-field region near the drain. The known phenomenon that buried-channel (BC) PMOS has higher hot-electron injection probability but lower channel field (I_SUB/I_D) than a similar surface-channel (SC) device is successfully modeled. This phenomenon can be attributed to the larger energy band hump-up near the drain and the larger oxide field (and thus greater barrier lowering) at a given bias condition for the buried-channel device. The I_G characteristics can be obtained from the calculated I_G /I_SUB ratio, using readily available I_SUB values     

Effects of localized interface defects caused by hot-carrier stressin n-channel MOSFETs at low temperature

Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V_d=5.5 V and gate voltage V_g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG_m and threshold voltage shift ΔV_t, do not occur at the same V_g. As well, ΔK_t is very small for the V_g <V_d stress regime, becomes significant at V_g≈V_d, and then increases rapidly with increasing V_g, whereas ΔG_m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress     

Gate current in OFF-state MOSFET

The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-Å or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I_D walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure     

A coupled study by floating-gate and charge-pumping techniques ofhot carrier-induced defects in submicrometer LDD n-MOSFET's

The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V_d/8 to V_d) by hot-hole and/or hot-electron injections, and their generation rates (10^-9 and 10^-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I_d-V_g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I _d-V_g degradation     

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe     

Electrical properties of MOSFET's with N2O-nitridedLPCVD SiO2 gate dielectrics

Electrical properties of MOSFETs with gate dielectrics of low-pressure chemical-vapor-deposited (LPCVD) SiO₂ nitrided in N₂O ambient are compared to those with control thermal gate oxide. N₂O nitridation of CVD oxide, combines the advantages of interfacial oxynitride growth and the defectless nature of CVD oxide. As a result, devices with N₂O-nitrided CVD oxide show considerably enhanced performance (higher effective electron mobility), improved reliability (reduced charge trapping, interface state generation, and transconductance degradation), and better time-dependent dielectric breakdown (TDDB) properties (t_BD ) compared to devices with control thermal oxide     

Examination of oxide damage during high-current stress of n-MOStransistors

Damage to n-channel MOSFETs under different levels of drain current stress is compared. It is shown that the post-stress I _d-V_gs characteristics show distinctly different behavior for different stresses. These differences are interpreted in terms of the location of the stress damage along the Si-SiO₂ interface. It is shown that damage from low drain current stress occurs at the Si-SiO₂ interface just inside the drain junction, under strong gate control. Damage from high drain current stress occurs at the Si-SiO₂ interface deeper inside the drain junction region, under weak gate control. The damage localization interpretation is supported by simulations and by localized Fowler-Nordheim injection experiments. It is further shown that at intermediate levels of drain current injection, the damage occurs at the Si-SiO₂ interface in both drain regions. The differences are explained in terms of the bipolar action at high drain current levels, which forces the channel charge away from the Si-SiO₂ interface at the drain junction edge     

Nonlinear GaAs MESFET modeling using pulsed gate measurements

The effects of traps in GaAs MESFETs are studied using a pulsed gate measurement system. The devices are pulsed into the active region for a short period (typically 1 μs) and are held in the cutoff region for the rest of a 1-ms period. While the devices are on, the drain current is sampled and a series of pulsed gate I-V curves are obtained. The drain current obtained under the pulsed gate conditions for a given V_GS and V_DS gives a better representation of the instantaneous current for a corresponding V_gs and V_ds in the microwave cycle because of the effects of traps. The static and pulsed gate curves were used in a nonlinear time-domain model to predict harmonic current. The results showed that analysis using pulsed gate curves yielded better predictions of harmonic distortion than analysis based on conventional state I-V curves under large-signal conditions     

Hot-carrier-induced degradation of gate dielectrics grown innitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N₂ O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g_m had a 15×improvement over control oxides not grown in a N₂O atmosphere. Further improvement in g_m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO₂ interface, leading to lower interface state generation (ISG). Improvements were also observed in I_g-V_g characteristics, indicating a reduction of trap sites both at the Si/SiO₂ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N₂O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N ₂O oxides and is a subject for further study     

A recessed-gate InAlAs/n+-InP HFET with an InP etch-stoplayer

The authors have exploited both the attractive transport properties and the etch selectivity of InP in a novel InAlAs/n⁺ -InP metal-insulator-doped-channel heterostructure FET (MIDFET). In several other material systems, the MIDFET has been shown to be well-suited to high-power telecommunications applications. The device employs InP both as the channel layer and as an etch-stop layer in a selective-etch recessed-gate process. L_g=1.8-μm devices achieve g_m and I_D,max values of 224 mS/mm and 408 mA/mm, respectively, the highest recorded values for an InP channel HFET with L_g⩾0.8-μm, including MODFETs. These figures combine with a breakdown voltage of 10 V and peak values of f _T and f_max of 10.5 and 28 GHz, respectively. The selective-etch recessed-gate process contributes to excellent device performance while maintaining a tight 60-mV threshold voltage distribution (13 mV between adjacent devices)     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

Doubly strainedIn0.41Al0.59As/n+-In0.65Ga0.35As HFET with high breakdown voltage

An In_0.41Al_0.59As/n⁺-In_0.65 Ga_0.35As HFET on InP was designed and fabricated, using the following methodology to enhance device breakdown: a quantum-well channel to introduce electron quantization and increase the effective channel bandgap, a strained In_0.41Al_0.59As insulator, and the elimination of parasitic mesa-sidewall gate leakage. The In_0.65Ga_0.35As channel is optimally doped to N_D=6×10¹⁸ cm^-3. The resulting device (L_g=1.9 μm, W_g =200 μm) has f_t=14.9 GHz, f_max in the range of 85 to 101 GHz, MSG=17.6 dB at 12 GHz V_B=12.8 V, and I_D(max)=302 mA/mm. This structure offers the promise of high-voltage applications at high frequencies on InP