Initial and boundary conditions in multidimensional wave digital filter algorithms for plate vibration

Recently, multidimensional wave digital filter (MDWDF) structures have been proposed for the modeling of plate vibration problems. In this paper, we discuss how initial and boundary conditions may be properly embedded into such an algorithm in terms of the state quantities that are an integral part of the algorithm. Due to the essential feature of fully-local interconnectivity in the MDWDF model, different types of boundary conditions can be easily satisfied in a very simple and efficient manner. Instead of remodifying the whole algorithm, usually required by finite elements based methods, boundary conditions in terms of state outputs are simply attached to the model. This feature is especially useful when dealing with the mixed-edges boundary conditions frequently encountered in practice. Graphical results obtained from implementing the MDWDF algorithm are given to further demonstrate the capacities of the method in efficiently handling a fourth-order Mindlin plate vibration system with various types of boundary conditions.     

Serial block pipelined wave digital filter

Based on serialising a previously established block pipelined architecture for PCAS wave digital filters, a lower transistor count, lower power implementation is derived     

Top-down design of a VLSI digital filter bank

This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.     

基于MATLAB的FIR滤波器的设计

基于MATLAB信号处理工具箱,设计一种滤波器,针对信号的分离和滤除,要求有良好的幅频特性和线性相位特性,且可通过参数来改变其主瓣宽度和旁瓣衰减。提出基于窗函数法设计滤波器,加入信号源,利用FDATool设计和分析模块电路,经过Simulink仿真,对其进行时域、频域分析和滤波。实验结果表明,本设计方法能够有效的滤除无...     

Minimizing quantization effects in a practical second-order digital filter bank

The paper describes the solution to coefficient and product-quantization effects in a practical, real-time digital filter bank. The solution to the coefficient-quantization effects involves simple manipulation of the floating-point filter coefficients. A computer simulation of product-quantization errors enables the appropriate number of bits for the truncated products to be determined.     

A multidimensional nonlinear edge-preserving filter for magneticresonance image restoration

The paper presents a multidimensional nonlinear edge-preserving filter for restoration and enhancement of magnetic resonance images (MRI). The filter uses both interframe (parametric or temporal) and intraframe (spatial) information to filter the additive noise from an MRI scene sequence. It combines the approximate maximum likelihood (equivalently, least squares) estimate of the interframe pixels, using MRI signal models, with a trimmed spatial smoothing algorithm, using a Euclidean distance discriminator to preserve partial volume and edge information. (Partial volume information is generated from voxels containing a mixture of different tissues.) Since the filter's structure is parallel, its implementation on a parallel processing computer is straightforward. Details of the filter implementation for a sequence of four multiple spin-echo images is explained, and the effects of filter parameters (neighborhood size and threshold value) on the computation time and performance of the filter is discussed. The filter is applied to MRI simulation and brain studies, serving as a preprocessing procedure for the eigenimage filter. (The eigenimage filter generates a composite image in which a feature of interest is segmented from the surrounding interfering features.) It outperforms conventional pre and post-processing filters, including spatial smoothing, low-pass filtering with a Gaussian kernel, median filtering, and combined vector median with average filtering.     

Exploiting the parallelism of multidimensional wave digital algorithms on multicore computers

Multidimensional wave digital algorithms for numerical integration of partial differential equations exhibit not only important robustness properties, but also a massive amount of parallelism. As the technology limit of heat dissipation stalls a further increase of clock rates, modern CPUs incorporate multiple cores for parallel computation. In this paper, a safe and efficient multithreading concept is presented to exploit the multicore architecture for multidimensional wave digital algorithms. Context switching and synchronization overhead is investigated as well as effects of unfair operating system thread scheduling due to unequal cache sharing of cores. Simulation results for the nonlinear Euler equations confirm the efficiency of the proposed setup on a 1-core, 4-core and a 2 × 4-core system.     

Technique for flexible multidimensional filter design

This new design technique utilises one-dimensional half-band filter units arranged in a tree structure to split multidimensional frequency space into sections. These sections may be switched in or out to form an approximation to any desired frequency response. The technique has proved useful in television bandwidth reduction experiments using subsampling.     

A multiplexed switched capacitor filter bank

A technique is introduced which allows several integrator capacitors to be multiplexed onto a single operational amplifier. As a result, the op amp can be shared by several switched capacitor filter channels, drastically reducing the number of op amps required for filter banks. Twenty second-order filters have been implemented in a circuit using only two op amps and 2.5 mm/SUP 2/. The design of this system is presented and its performance is discussed. Some loss of signal energy is shown to occur during the multiplexing operations, which reduces filter Q. Causes of this charge loss are described, and its effects on performance are modeled. The design of the op amp used is presented, which incorporates a new system of input stage biasing and differential to single-ended conversion, as well as other features.     

Optimal synthesis of multidimensional state-space digital filters: A general analysis

The optimal synthesis of a single-input single-output (SISO) multidimensional (M-D) digital filter with fixed-point arithmetic is investigated. The necessary and sufficient conditions for optimal realizations for both optimal and equal wordlength registers are established. It is shown that these optimality conditions always can be satisfied for an arbitrary M-D filter. It is proven that optimal structures possess some favorable properties such as low coefficient sensitivity. It is found that the optimal realizations of a multidimensional filter demonstrate a remarkable property in needed number of multipliers per sample output is comparison to one dimensional (1-D) optimal structures. Two numerical examples are presented to illustrate the design procedure and usefulness of the proposed scheme.     

A simple odd-symmetric filter for digital broadcasting

A new odd-symmetric filter for ISI suppression and VSB transmission is proposed. The frequency response of the proposed filter is similar to that of an ideal raised-cosine filter, but in contrast to raised-cosine the new filter is realizable, e.g. using simple active filters. Simulation results show that concerning ISI suppression the new filter is significantly more efficient than the classical Butterworth or Chebyshev filters. The proposed filter can be also used as a VSB filter for TV modulators and demodulators.     

A digital signal-processing codec filter for PCM applications

A programmable signal-processing codec filter (SICOFI) which performs its main filter functions by means of digital signal processing (DSP) is described. Besides PCM coding and band limitation, the circuit provides programmable adjustment of level control, impedance matching, hybrid balancing, and frequency response correction. Circuit performance, chip area, and power consumption have been optimized and a set of consistent CAD tools were developed for complete verification. Progress in circuit-design simulation techniques and an advanced CMOS technology allowed the economic integration of the analog and digital parts consisting of 36000 transistors on a 37.5-mm/SUP 2/ die.     

Numerical integration of partial differential equations using principles of multidimensional wave digital filters

Physical systems described by partial differential equations (PDEs) are usually passive (due to conservation of energy) and furthermore massively parallel and only locally interconnected (due to the principle of action at proximity, as opposed to action at a distance). An approach is developed for numerically integrating such PDEs by means of algorithms that offer massive parallelism and require only local interconnections. These algorithms are based on the principles of multidimensional wave digital filtering and amount to directly simulating the actual physical system by means of a discrete passive dynamical system. They inherit all the good properties known to hold for wave digital filters, in particular the full range of robustness properties typical for these filters.In this paper, only the linear case is considered, with particular emphasis on systems of PDEs of hyperbolic type. The main features are explained by means of an example.     

A refined motion estimation strategy for adaptive interpolation filter

Adaptively selecting the filter coefficients for interpolating fractional pixels (sub-pel) can significantly improve the quality of reference pictures. However, the complexity of implementation is greatly increased by performing motion estimation (ME) and mode decision (MD) for multiple passes. This paper briefly introduces the adaptive interpolation filter (AIF) technique and proposes a refined ME strategy for realizing the AIF process with low complexity. By using this method, the 2-pass encoding procedure can be avoided while the coding efficiency of the AIF is maintained. The proposed method is implemented and verified on the AVS video software platform.     

A simple sufficient criterion for the stability of multidimensional digital filters

In this paper a theorem concerning the absence of zeros of a multivariable polynomial in the closed unit polydisc of a multidimensional complex plane is presented. Using this theorem the stability of a large class of multidimensional digital filters can be tested almost by inspection.     

A note on digital filter synthesis

It is commonly assumed that digital filters with both poles and zeros in the complex z-plane can be synthesized using only recursive techniques while filters with zeros alone can be synthesized by either direct convolution or via the discrete Fourier transform (DFT). In this letter it is shown that no such restrictions hold and that both types of filters (those with zeros alone or those with both poles and zeros) can be synthesized using any of the three methods, namely, recursion, DFT, or direct convolution.     

A recursive digital MTI radar filter

An approach for designing a recursive digital MTI radar filter in the z plane is described. The resultant filter exhibits a sharp spectrum rolloff and an almost flat passband in the amplitude response.     

A low-power digital matched filter for direct-sequencespread-spectrum signal acquisition

This paper presents a low-power 128-tap dual-channel direct-sequence spread-spectrum (DSSS) digital matched-filter chip. Design techniques used to reduce the power consumption of the system include latch-based register file filter structure, a high-rate compression scheme, optimized compressor cells, and semicustom layout design. To further reduce the power consumption and the hardware requirement of the clock tree, a double-edge-triggered clocking scheme is adopted. The proposed chip is fabricated using a 0.8-μm standard CMOS process. As the experimental results of the chip indicate, the matched filter can operate at 50 MHz and dissipates 184 mW at 5-V supply voltage. The supply voltage can be scaled down to 2 V for lower speed applications. As a consequence, the proposed design has low power consumption and can be used for code acquisition of DSSS signals in portable systems     

A low-pass digital optical filter for optical fiber communications

A passive, all-optical fiber device that limits the rate at which digital information can be transmitted over a single-node fiber is described. Experimental results that demonstrate the frequency response of the device and its effect on baseband intensity-modulated digital transmission are presented. A variety of issues related to the performance of these devices is discussed     

A high-speed digital filter LSI for video signal processing

A ninth-order symmetrical filter has been developed for use in two-dimensional (2-D) processing in TV video systems, especially in high-definition TV receivers. A 2-D filter that is composed of only two types of LSIs (one-dimensional (1-D) digital filter LSI and delay-line) is discussed. The architecture of the digital filter LSI and circuit techniques are presented to obtain high-speed operation, to save chip area, and to decrease power consumption. The order and the transfer function of the filter can be altered by means of the external terminals. The chip, achieved through 2-/spl mu/m CMOS technology, contains about 52000 transistors and occupies an area of 50 mm/SUP 2/. It operates at a high clock frequency of over 33 MHz, and dissipates only 600 mW of power.