Design and modeling of high-resolution multibit log-domain \Delta \Sigma modulators

Log-domain Delta-Sigma ( $\Delta \Sigma$ ) modulators are attractive for implementing analog-to-digital (A/D) converters (ADCs) targeting low-power low-voltage applications. Previously reported log-domain $\Delta \Sigma$ modulators were limited to 1-bit quantization and, hence, could not benefit from the advantages associated with multibit quantization (namely, reduced in-band quantization noise, and increased modulator stability). Unlike classical $\Delta \Sigma$ modulators, directly extending a log-domain $\Delta \Sigma$ modulator with a 1-bit quantizer to a log-domain $\Delta \Sigma$ modulator with a multibit quantizer is challenging, in terms of CMOS circuit implementation. Additionally, the realization of log-domain $\Delta \Sigma$ modulators targeting high-resolution applications necessitates minimization of distortion and noise in the log-domain loop-filter. This paper discusses the challenges of multibit quantization and digital-to-analog (D/A) conversion in the log-domain, and presents a novel multibit log-domain $\Delta \Sigma$ modulator, practical for CMOS implementation. SIMULINK models of log-domain $\Delta \Sigma$ modulator circuits are proposed, and the effects of various circuit non-idealities are investigated, including the effects of log-domain compression–expansion mismatch. Furthermore, this paper proposes novel low-distortion log-domain analog blocks suitable for high-resolution analog-to-digital (A/D) conversion applications. Circuit simulation results of a proposed third-order 3-bit class AB log-domain $\Delta \Sigma$ loop-filter demonstrate 10.4-bit signal-to-noise-and-distortion-ratio (SNDR) over a 10 kHz bandwidth with a $0.84\,V_{pp}$ differential signal input, while operating from a 0.8 V supply and consuming a total power of $35.5\,\upmu \hbox {W}.$      

The First Year Nursing Students’ Achievement and Critical Thinking in Local Wisdom Course Using Problem Based Learning Process

The purpose of this one group—pre test post test design classroom research was to examine learning achievement, critical thinking and satisfaction of first year nurse students at school of nursing during academic year 2011. In the research activity, 94 students participated in three weeks for each scenario in Local Wisdom and Health Care which composed of 4 scenarios. Problem based learning process were included the preparation of facilitators, preparation of learners, and problem/scenario based assignments. The instruments composed of 1) 135 items, 4 multiple choices test which were covered behavioral objectives and blue print of test and validated by course lecturers 2) opinion evaluation form, open ended questionnaire and 3) the critical thinking questionnaire, 80 items in five domains which are Inference, Recognition of Assumption, Deduction, Interpretation, and Evaluation of Argument with internal consistency of .73. Data were analyzed using frequency, percentage, mean, standard deviation, percentile, t test and $\chi ^{2}$ test. It was found that the highest score of learning achievement was 88.79 % while the lowest score was 70.33 %, average learning achievement score was 80.60 $(\pm 3.47)\%$ . The highest grade levels were B+ and B equally (41.49 %). Students demonstrated higher overall critical thinking $(49.62 \pm 5.78)$ after undergone problem based learning process than before the problem based learning process $(46.69 \pm 6.00)$ statistically significance $(\text{ t}\,=\,4.443, p\,<\,.05)$ . Inference and Recognition of Assumption domain after PBL process were better than their own thoughts before PBL process significantly (t = 2.288, $p\,<\,.05$ ; t = 6.287, $p\,<\,.05$ , respectively). The ability of critical thinking was found that the high, moderate and low level (percentile $>75, 25-75$ and $<25$ ) after PBL were difference from the ability before the process significantly $(\chi ^{2}=12.219, p\,<\,.05)$ .     

Six Order Cascaded Power Line Notch Filter for ECG Detection Systems with Noise Shaping

This paper presents the design of an operational transconductance amplifier-C (OTA-C) notch filter for a portable Electrocardiogram (ECG) detection system. A six order cascaded filter is utilized to reduce the effect of the power line interference at (50/60 Hz). The proposed filter is based on a programmable balanced OTA circuit. Based on this, PSPICE post layout simulation results for the extracted filter using 0.25  \(\upmu \) m technology and operating under \(\pm \) 0.8 V voltage supply are also given. The six order notch filter provides a notch depth of 65 dB (43 dB for 4th order), input referred noise spectral density with noise shaping of 9  \(\upmu \) Vrms/ \(\surd \) Hz at the pass band frequencies and 9 mVrms/ \(\surd \) Hz at the notch (zero) frequency which provide noise shaping for the ECG signal. These results demonstrate the ability of the filter to be used for ECG signal filtering which is located within 150 Hz.     

Soft X-ray Absorption and Photoemission Spectroscopy Study of Cobalt-Based Thermoelectric Oxides: \hbox{Ca}_3\hbox{Co}_4\hbox{O}_9, \hbox{Ca}_3\hbox{Co}_2\hbox{O}_6, and \hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}

The electronic structures of Co-based potential thermoelectric (TE) oxides, including $\hbox{Ca}_3\hbox{Co}_4\hbox{O}_9$ and $\hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}$ (y = 8 + δ) single crystals and polycrystalline $\hbox{Ca}_3\hbox{Co}_2\hbox{O}_6$ , have been investigated by employing soft x-ray absorption spectroscopy (XAS) and photoemission spectroscopy (PES). Co 2p XAS measurements show that Co ions are nearly trivalent ( $\hbox{Co}^{3+}$ ) in all of these Co-based TE oxides with a small mixture of $\hbox{Co}^{4+}$ ions in $\hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}$ . Valence-band PES and O 1s XAS measurements show that the occupied Co 3d states are located at the top of the valence bands and that the lowest unoccupied states have the primarily Co 3d character, respectively. These findings suggest the importance of the Co 3d electronic structures in determining TE properties of these Co-based oxides.     

Extended Robust \mathcal{H}_{2} and \mathcal{H}_{\infty} Filter Design for Discrete Time-Invariant Linear Systems with Polytopic Uncertainty

This paper is concerned with the problem of robust $\mathcal{H}_{2}$ and $\mathcal{H}_{\infty}$ filter design for discrete-time linear time-invariant systems with polytopic parameter uncertainties. Less conservative robust $\mathcal{H}_{2}$ and $\mathcal{H}_{\infty}$ filter design procedures are proposed in terms of single-parameter minimization problems with linear matrix inequality constraints. To this end, we generalize the filter structures available in the literature to date in such a way that the filter’s next state is built by summing the filter’s states over several samples from the past to the present. For stability of the filtering error system, the homogeneous polynomial parameter-dependent Lyapunov functions are employed. Finally, illustrative examples are given to demonstrate the merits of the proposed methods.     

WCDMA Multiclass Downlink Capacity and Interference Statistics of Cigar-Shaped Microcells in Highways

In this paper, the multiclass downlink capacity and the interference statistics of the sectors of a cigar-shaped microcells using wideband code-division multiple-access with soft handover mode are analyzed. The two-slope propagation model with log-normal shadowing is used in the analysis where a model of 8 cigar-shaped microcells is utilized. The performance of the downlink is studied for different [sector range R, standard deviation of the shadowing ( $\sigma _{1}$ and $\sigma _{2})$ and propagation exponents ( $\text{ s}_{1}$ and $\text{ s}_{2})$ ]. It is found that increasing the sector range from 500 to 1,000 m will increase the sector downlink capacity. Also, it is found that increasing the value of the propagation parameters ( $\sigma _{1}$ and $\sigma _{2})$ will reduce the downlink sector capacity. It is noticed that, the effect of changing the propagation exponent $\text{ s}_{1}$ is null while increasing the propagation exponent $\text{ s}_{2}$ will increase the downlink capacity.     

Effect of the stoichiometric composition of the Si(111)\sqrt {21} × \sqrt {21} -(Au, Ag) surface phase on substrate conductivity

The conductivity of a silicon substrate with a Si(111) $\sqrt {21} $ × $\sqrt {21} $ -(Au, Ag) surface phase is studied. It is found that the surface conductivity of such a substrate varies depending on the ratio of the amounts of gold and silver in the given structure. An analysis of the behavior of the Si(111) $\sqrt {21} $ × $\sqrt {21} $ -(Au, Ag) surface conductivity during silver adsorption indicates the effect of a space-charge layer in the surface region of the substrate on the measurement results.     

A 5 GHZ CMOS Power VCO with Novel Frequency-Modulation for RF Transmitter

A 5 GHz transformer-feedback power oscillator with novel frequency modulation (FM) up to 10 MHz is presented in this paper. The novel FM is achieved by a CMOS transistor between transformer and ground, which is designed for varying the equivalent inductance and mutual inductance of the transformer and shows no DC connection with the oscillation circuit. The major frequency tuning is realized by the variable capacitor which is controlled by a phase lock loop. The RF VCO with 210 MHz tuning range operates in class-E mode to achieve a cost-effective transmitter, which demonstrates a high DC-to-RF conversion efficiency of 39 %. A RF power of 15.1 dBm and phase noise better than \(-\) 109 dBc/Hz @ 100 kHz from the central frequency of 5.5 GHz is obtained with the biasing conditions V \(_\mathrm{ds}\) = 1.8 V and V \(_\mathrm{gs}\) = 0.65 V. The VCO also demonstrates an ultra-low voltage operation capability: with V \(_\mathrm{ds}\) = V \(_\mathrm{gs}\) = 0.6 V and DC power consumption of 9 mW, the output power is 4.5 dBm and the phase noise better than \(-\) 93 dBc/Hz @ 100 kHz. The die size of the transformer-feedback power oscillator is only \(0.4\times 0.6\) mm \(^{2}\) .     

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of \(512\times 36\) of E-TCAM has been successfully implemented on Xilinx Virtex- \(5\) , Virtex- \(6\) , and Virtex- \(7\) field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains \(33.33\)  % reduction in block-RAMs, \(71.07\)  % in slice registers, \(77.16\)  % in lookup tables, \(53.54\)  % in energy/bit/search, and offers \(63.03\)  % improvement in speed, compared with the best available SRAM-based TCAM designs.     

Analysis of CDMA MIMO Beamforming Multicell Deployment Scenarios using Effective Radiation Patterns

This paper presents approximate formulas for the signal to interference ratio (SIR) gain and the corresponding bit error rate (BER) performance, when the simple concept of an effective radiation pattern of the produced ‘real world’ Multiple-Input-Multiple-Output (MIMO) beamforming radiation pattern, is considered for CDMA multi-cell/tier deployments. These simple and practical formulas can be easily used to produce initial results for a range of effective values corresponding to different operational scenarios, and hence, provide a fast and straightforward approach to evaluate performance aspects of MIMO beamforming multicell deployments. Results show that for macrocellular operational scenarios with $10^{\circ }$ effective beamwidth and $-$ 10 dB effective average sidelobe level, 11 dB SIR gain and 3.5 orders of magnitude BER improvement (compared to the omnidirectional scenario) can be achieved with an aggressive (MIMO beamforming in all cells) deployment strategy.     

Demonstration of using multi-band 16-QAM OFDM modulation with direct-detection in 10 GHz bandwidth for 37.3-Gb/s PON

We propose and experimentally demonstrate a 37.3 Gb/s passive optical network using four-band orthogonal-frequency-division-multiplexing (OFDM) channels within 10 GHz bandwidth. Here, the required sampling rate and resolution of digital-to-analog/analog-to-digital (DA/AD) converter are only 5 GS/s and 8 bits to accomplish the 40 Gb/s OFDM downstream rate. Moreover, to reduce the power fading and fiber chromatic dispersion issues, a $-$ 0.7 chirp parameter Mach-Zehnder modulator is used for the four-band OFDM modulation scheme. Downstream negative power penalty of $-$ 0.37 dB can be obtained at the bit error rate of $3.8\times 10^{-3}$ after 20 km standard single mode fiber transmission without dispersion compensation.     

A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 \upmu \hbox {m} CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5–3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18  \(\upmu \hbox {m}\) technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than \(-\) 11.6, output return loss of \(-\) 19.2 to \(-\) 19 and reverse isolation of \(-\) 38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.     

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( \(\sim \) 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage \(V_\mathrm{L}\) ( \(\sim \) 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ \(V_\mathrm{DD})^{ 2 }\,\times \) 100 %) due to reduced voltage swing (from \(V_\mathrm{DD }\)  = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a \(256 \times 64\) bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.     

Efficient Reverse Converters for 4-Moduli Sets {2^{2n-1}-1, 2^{n}, 2^{n}+1, 2^{n}-1} and {2^{2n-1}, 2^{2n-1}-1, 2^{n}+1, 2^{n}-1} Based on CRTs Algorithm

Speed and complexity of a reverse converter are two important factors that affect the performance of a residue number system. In this paper, two efficient reverse converters are proposed for the 4-moduli sets {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } and {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } with 5 \(n\) -bit and 6 \(n\) -bit dynamic range, respectively. The proposed reverse converter for moduli set {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed based on CRT and New CRT-I algorithms and in two-level structure. Also, an efficient reverse converter for moduli set {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed by applying New CRT-I algorithm. The proposed reverse converters are based on adders and hence can be simply implemented by VLSI circuit technology. The proposed reverse converters offer less delay and hardware cost when compared with the recently introduced reverse converters for the moduli sets {2 \(^{n}+1\) , 2 \(^{n}-1\) ,2 \(^{n}\) , 2 \(^{2n+1}-1\) } and {2 \(^{n}+1\) , 2 \(^{n}-1\) , 2 \(^{2n}\) , 2 \(^{2n+1}-1\) }.     

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-\Updelta\Upsigma ADC with 1.5 cycle quantizer delay and improved STF

A 1 GS/s continuous-time delta-sigma modulator (CT- $\Updelta\Upsigma$ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- $\Updelta\Upsigma$ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- $\Updelta\Upsigma$ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.     

A Wide Tuning Range Voltage Controlled Oscillator with a High Tunable Active Inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator (VCO) with a high-tunable active inductor circuit. In this VCO circuit, the coarse frequency is achieved by tuning the integrated active inductor circuit. The VCO circuit is designed in 0.18  \(\upmu \hbox {m}\) CMOS process and simulated with Cadence Spectra. The simulation results show the frequency tuning range from 120 MHz to 2 GHz resulting in a tuning range of 94 %. The phase noise variation is from \(-\) 80 to \(-\) 90 dBc/Hz at a 1 MHz frequency offset, and output power variation is from \(-\) 4.7 to \(+\) 11.5 dBm. The active inductor power consumption is 2.2 mW and the total power dissipation is 7 mW from a 1.8 V DC power supply. By comparing the proposed VCO circuit with the general VCO topology, the results show that this VCO architecture by using the novel, high-tunable and low power active inductor circuit, presents a better performance regarding low chip size, low power consumption, high tuning range and high output power.     

A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor

This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using \(0.18\,\upmu \hbox {m}\) CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential active inductor (DAI) circuit and cross-coupled current injection technique within the conventional double-balanced Gilbert cell mixer. A cross-coupled current bleeding circuit is used to inject the current to the switching stage to decrease the flicker noise. Instead of spiral inductor, a DAI with high tunability of the inductor and quality factor is used to tune out the parasitic capacitance effect and decrease the leakage current that has a harmonic component and produce the flicker noise. By tuning the DAI, the flicker noise corner frequency is reduced to 150 Hz. The proposed circuit is simulated with Cadence Spectra and the simulation results shows the NF of 11.2 dB, conversion gain of 23.7 dB and IIP3 of \(-6\)  dB for an RF frequency of 2.4 GHz. The excellent LO-RF, LO-IF, RF-LO and RF-IF isolations of \(-60, -110, -52\) and \(-64\)  dB are achieved respectively. The total power consumption is 10.5 mW from a 1.8 V DC power supply.     

Statistical Analysis of Cognitive Radio Operation in a Periodic Pattern of Sensing and Transmission

A Cognitive Radio must sense the channel to detect spectrum holes. To this end, it senses the channel for $T_S$ and transmits its data for $N T_S$ , if the channel is not occupied by Primary User. It is expected that the more frequent arrivals of PU, characterized by the arrival rate $\lambda $ , provides CR with less opportunity. The aim of this paper is two-fold: analysis of the interaction between $N$ and $\lambda $ , as well as the access time of CR on the one hand and study of the possible benefits a variable decreasing modulation order might provide for CR on the other. In both cases, data rate of CR and the interference it causes for PU are considered as the performance measures.     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

Chaotic dynamics of the fractional order nonlinear system with time delay

This paper presents the fractional order model of a nonlinear autonomous continuous-time difference-differential equation with only one variable. Numerical simulation results of the fractional order model demonstrate the existence of chaos when system order $q\ge 0.2$ . Values of the delay time $\tau $ in which chaotic behavior is observed at system order $q$ are quantitatively defined using the largest Lyapunov exponents obtained from the output time series.