A low power CMOS phase-switching prescaler for 1.8–2.4 GHz wireless communications

A divide-by-31/32 phase switching prescaler with a simple divide-by-4 multi-phase ring counter is presented. By using this divide-by-4 unit, a low power consumption is obtained while a wide range operation is maintained. Fabricated with a standard 0.18 μm CMOS technology, the prescaler can work properly from 1.8 to 3.1 GHz with a maximum current dissipation of 1.3 mA from a 1.8 V supply voltage. It can cover most of wireless communication standards in 1.8/1.9 GHz and 2.4 GHz bands.     

A 3 Gb/s transmitter with a tapless pre-emphasis CML output driver

A 3 Gb/s wireline transmitter (Tx) with a tapless pre-emphasis current-mode logic output driver is presented in this paper. The proposed output driver can support 2.5, 6 and 10 dB pre-emphasis without any additional current tap. It can reduce the current consumption of the output driver by 30 %. The 1.5 GHz phase-locked loop (PLL), multi-phase generator, and 26-to-1 serializer are utilized to serialize 26-bit parallel data to 1-bit 3 Gb/s serial data stream. The rms and peak-to-peak jitters of PLL are 2.97 and 22.5 ps, respectively. The eye opening of the proposed output driver at 3 Gb/s is 0.8UI with a 10 dB loss channel. The current consumption of the output driver is only 5.14 mA, and the Tx is 9 mA. The area of the Tx is 0.72 mm² using the 0.11 μm CMOS process.     

A novel 2.2 Gbps LVDS driver circuit design based on 0.35μm CMOS

This paper presents a novel high-speed low voltage differential signaling(LVDS) driver design for point-to -point communication.The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased.A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage.The proposed driver was implemented in a standard 0.35μm CMOS process with a die area of 0.15 mm~2.The test result show...     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low data rate applications

A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of ?92 dBm for a 10^?3 BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).     

A high-speed rail-to-rail output buffer with push–pull dual-path and dynamic-bias for LCD driver ICs

The design of a low-power high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time; the proposed output buffer thus has a push–pull dual-path function for high-speed operation. Since a conventional class-AB output stage requires two bias voltages, the proposed output buffer provides two dynamic bias voltages to increase the transient response of the class-AB output stage. The two dynamic biases use only two transistors and do not increase the quiescent current. The proposed output buffer is implemented on standard 0.35 μm CMOS 2-poly 4-metal process technology and simulated using HSPICE. The power consumption is 23.1 μW, with settling times of 0.7 and 0.68 μs for rising and falling edges, respectively, under a 1000 pF load. The active area of the output buffer amplifier is only 48 × 48 μm².     

A low power passive-active ΔΣ modulator with high-resolution employing an integrator with open-loop unity-gain buffer

This paper presents a new passive-active ΔΣ modulator with high-resolution and low-power applications. An open-loop unity gain buffer is used to improve the performance of a passive switch capacitor integrator. Since this technique compensates phase and gain errors, there is no need for large capacitors, which result in a great reduction in the chip footprint. The first filter is passive, so the output swing of the amplifier is small but large enough to guarantee the linearity and a relaxed slew rate in the modulator structure, which leads to the low power. Using the second-order modulator with an adequate oversampling ratio leads to the desired SNR. The post-layout simulation of the second-order passive-active modulator is performed in Spectre/Cadence electrical simulator using TSMC 0.18 CMOS model in the standard 0.18 μm CMOS process. The dynamic range of 92.4 dB, peak signal to noise ratio of 88.6 dB, peak signal to noise plus distortions of 82.7 dB were achieved while consuming 1.93 μw in a 500 Hz signal bandwidth at 1.5 V supply, giving a FoM_Walden of 0.173 pJ/ conv-step and the FoM_Schreier is 176.53 dB.     

CMOS implementation of a 1.6 GHz low voltage low phase noise quadrature output frequency synthesizer with automatic amplitude control

This article presents the design of a 1.2 V CMOS low phase noise quadrature output frequency synthesizer (FS) to be used for a GPS tuner application. Special reference is made to the design of a wide tuning range quadrature output voltage-controlled oscillator which is equipped with an automatic amplitude controller. It exhibits a phase noise response of less than −115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 36%. The effect of the automatic amplitude control is shown to improve phase noise at high oscillation frequencies and its noise has a negligible effect on the phase noise response even at low offset frequencies from the carrier. Preliminary analysis is presented showing the negligible effect of a DC–DC converter on the spurious level of the FS, included to permit the use of low sensitivity varactors. Design guidelines for reducing both the loop noise and the AM-to-PM conversion factors of the oscillator are also given. The design was made using the STMicroelectronics 0.13 μm HCMOS9-RF technology design kit.     

A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18 μm CMOS process. The measurement results show that the random noise (RN) is 7e_rms⁻, the pixel conversion gain is 100 μV/e⁻. Since the measured full well capacity of the pixel is 25000e⁻, the CMOS image sensor achieves a 71 dB dynamic range (DR). The total power consumption at 60frame/s is 58.2 mW.     

5.18–7.42 GHz LC-VCO in subthreshold regime with low power low phase noise and immunity to PVT variations in 130 nm CMOS technology

In this paper, we propose an LC-VCO using automatic amplitude control and filtering technique to eliminate frequency noise around 2\(\omega _0\). The LC-VCO is designed with TSMC 130 nm CMOS RF technology, and biased in subthreshold regime in order to get more negative transconductance to overcome the losses in the LC-Tank and achieve less power consumption. The designed VCO operates at 5.17 GHz and can be tuned from 5.17 to 7.398 GHz, which is corresponding to 35.5% tuning range. The VCO consumes through it 495–440.5 \(\upmu\)W from 400 mV dc supply. This VCO achieves a phase noise of \(-\,122.3\) and \(-\,111.7\) dBc/Hz at 1 MHz offset from 5.17 and 7.39 GHz carrier, respectively. The calculated Figure-of-merits (FoM) at 1 MHz offset from 5.17 and 7.39 GHz is \(-\,199.7\) and \(-\,192.4\) dBc/Hz, respectively. And it is under \(-\,190.5\) dBc/Hz through all the tuning range. The FoM\(_T\) at 1 MHz offset from 5.17 GHz carrier is \(-\,210.6\) dBc/Hz. The proposed design was simulated for three different temperatures (\(-\,55\), 27, \(125\,^{\circ }\hbox {C}\)), and three supply voltages (0.45, 0.4, 0.35 V), it was concluded that the designed LC-VCO presents high immunity to PVT variations, and can be used for multi-standard wireless LAN communication protocols 802.11a/b/g.     

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.     

A wide output range voltage-mode buck converter with fast voltage–Tracking speed for RF power amplifiers

A high switching frequency voltage-mode buck converter with fast voltage-tracking speed, wide output range and PWM/PSM control strategy for radio frequency (RF) power amplifiers (PAs) has been proposed. To achieve the fast voltage-tracking speed, the maximum charging and discharging current control method has been used, and the filter inductor and capacitor values are reduced. A novel compensated error amplifier (EA) is presented to realize the wide output range. The investigated converter has been fabricated with GF 0.35 μm CMOS process and can operate at 5 MHz with the output voltage range from 0.6 V to 3.4 V. The experimental results show that the voltage-tracking speed can achieve 8.8 μs/V for up-tracking and 6 μs/V for down-tracking. Besides, the recovery time is less than 8 μs when the load change step is 400 mA.     

A high PSRR CMOS voltage reference with 1.2 V operation

A high power supply rejection ratio (PSRR) CMOS band-gap reference (BGR) with 1.2 V operation is proposed in this paper. The reference features include an error amplifier with a trimming circuit and a trimming resistor array on the chip. Local positive feedback is used in the error amplifier to obtain high gain. By trimming the resistor array, the PSRR of the error amplifier is trimmed around one to obtain a high PSRR. The trimming resistor array is controlled externally. The post simulation results indicate that the PSRR is up to ?130 dB@DC and ?89 dB@10 kHz. The experimental results show that, under a supply voltage of 1.2 V the measured PSRR is ?103 dB@dc and ?74 dB@10 kHz.     

A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range

A state variable block diagram method is given for the realization of universal biquadratic transfer functions employing second-generation current-controlled conveyors (CCCIIs). Using minimum number of passive components and properly adjusting the bias currents of CCCIIs, the proposed circuits can realize all the tunable frequency standard filter functions: high-pass, band-pass, low-pass, notch-pass, and all-pass by choosing appropriate input branches without changing the passive elements. These presented circuits are in current-mode and voltage-mode separately. The non-ideality analyses of these configurations are given. Additionally, a high-order low-pass filter derived from the proposed voltage-mode biquadratic filter is introduced. PSPICE simulation results are included to verify the theory.     

A novel ±0.8 V high-performance voltage-tunable CDTA with enhanced bandwidth

In this article, we propose a novel high-performance complementary metal oxide semiconductor (CMOS) current differencing transconductance amplifier (CDTA) with a transconductance gain (G_M) that can be linearly tuned by a voltage. By using a high-speed, low-voltage, cascaded current mirror active resistance compensation technique, the proposed CDTA circuit exhibits wide frequency bandwidths, high current tracking precisions as well as large output impedances. The linear-tunable G_M of the CDTA is designed with the use of linear composite metal oxide semiconductor field-effect transistor as basic cells in the circuit. Combining these two approaches, several design concerns are studied, including: impedance characteristic, tracking errors, offset and linearity and noise. The prototype chip with a 0.25 mm² area is fabricated in a GlobalFoundries’0.18 μm CMOS process. The simulated results and measured results with ±0.8 V DC supply voltages are presented, and show extremely wide bandwidths and wide linear tuning range. In addition, a fully differential band-pass filter for a high-speed system is also given as an example to confirm the high performance of the proposed circuit.     

A 0.5 V LC-VCO with improved varactor tuning technique for WSN

A 0.5 V LC-VCO implemented in 0.18 μm CMOS technology for wireless sensor network is described in this paper. An improved varactor tuning technique is proposed to decrease low frequency noise up-conversion and AM–FM phase noise of VCO, also it can increase Q of LC tank and reduce power consumption of VCO. For coarse tuning of VCO, it can increase the varactor control voltage variation range. For fine tuning of VCO, it can reduce the varactor nonlinearity. The measured tuning range is 4.58–5.26 GHz and power consumption is 2.2 mW. The measured phase noise is ?114 dBc/Hz at 1 MHz frequency offset from a 4.8 GHz carrier.     

A 5-bit lumped 0.18-μm CMOS step attenuator with low insertion loss and low phase distortion in 3–22 GHz applications

A 5-bit lumped CMOS step attenuator with low insertion loss and low phase distortion is designed and simulated in this paper. The proposed attenuator is based on lumped switched bridged-T and π structure attenuators, and implemented with 0.18-μm CMOS technology. Different attenuation states are controlled by NMOS switches. The switches in series branches have channel-shunt resistance to minimize the on-resistance without increasing parasitic capacitance. The NMOS switches in shunt branches are body-floated to improve the power handling performance of the proposed attenuator. Each attenuation module has an inductive phase-compensate low-pass network. The attenuator is controlled with a 5-bit digital signal to achieve the maximum attenuation amplitude range of 0–31 dB with 1 dB increase at 3–22 GHz. The root mean square (RMS) amplitude errors for each one of the 32 states are less than 0.53 dB and the RMS insertion phase is less than 6.3° at 3–22 GHz. The insertion loss is 5.5–13 dB, and the input P_1 dB is 18.4 dBm at 12.5 GHz.     

A 1-mW K-band gate AC-coupled VCO with 0.25 V supply voltage

A K-band low-voltage voltage controlled oscillator (VCO) implemented in standard 65-nm bulk CMOS process is proposed. By using the proposed gate AC-coupling technique and biasing the cross-coupled transistors in moderate inversion region, the oscillator core operates under ultra low supply voltage with acceptable current efficiency. Reverse short-channel effect is also employed to reduce the threshold voltage of the cross-coupled transistors. Operating from 23.1 to 24.8 GHz, the fabricated VCO is able to work under supply voltage as low as 0.25 V with a core power consumption of 1 mW.     

A high speed, low voltage to high voltage level shifter in standard 1.2 V 0.13 μm CMOS

The design of a high speed, low voltage to high voltage level shifter in a digital 1.2 V, 0.13 μm CMOS technology is presented. The topology uses two differentially switched cascoded transistor ladders. The output signal has an offset of two times the nominal supply voltage of the used technology with respect to the input signal. Oxide stress and hot carrier degradation is minimized since all transistors of the level shifter operate within the voltage limits imposed by the design rules of a mainstream CMOS technology.