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1.
The electrical transport properties of β-SiC/Si heterojunctions were investigated using current-voltage (I -V ) and capacitance-voltage (C -V ) characteristics. The heterojunctions were fabricated by growing n-type crystalline β-SiC films on p-type Si substrates by chemical vapor deposition (CVD). The I -V data measured at various temperatures indicate that at relatively high current, the heterojunction forward current is dominated by thermionic emission of carriers and can be expressed as exp(-qV bi/kT ) exp(V /ηkT ), where V bi is the built-in voltage of the heterojunction and η(=1.3) is a constant independent of voltage and temperature. At lower current, defect-assisted multitunneling current dominates. The effective density of states and the density-of-states effective mass of electrons in the conduction band of SiC are estimated to be 1.7×1021 cm -3 and 0.78m 0, respectively. This study indicates that the β-SiC/Si heterojunction is a promising system for heterojunction (HJ) devices such as SiC-emitter heterojunction bipolar transistors (HBTs) 相似文献
2.
Threshold voltage model for deep-submicrometer MOSFETs 总被引:9,自引:0,他引:9
Liu Z.-H. Hu C. Huang J.-H. Chan T.-Y. Jeng M.-C. Ko P.K. Cheng Y.C. 《Electron Devices, IEEE Transactions on》1993,40(1):86-95
The threshold voltage, V th, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V th on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V th dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined 相似文献
3.
Hot-carrier degradation of W gate PMOSFETs, which are surface-channel devices because of the work function of W, has been investigated in comparison with polycide (WSix/n+ poly-Si) ones. In W gate PMOSFETs, transconductance g m and threshold voltage V th decrease on the drain avalanche hot-carrier (DAHC) stress, and Δg m /g m0 and ΔV th become minimum at V G≅V D/2. By using the charge-pumping technique, it is found that, after stressing at the same stress condition, the interface state density of W gate devices is about 10 times larger than that of polycide ones but the densities of trapped electrons are almost equal. These results indicate that the difference of hot-carrier degradation between W and polycide gate devices is mainly caused by the difference of the interface state density 相似文献
4.
Peransin J.-M. Vignaud P. Rigaud D. Vandamme L.K.J. 《Electron Devices, IEEE Transactions on》1990,37(10):2250-2253
The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S I/I 2 versus the effective gate voltage V G=V GS-V off shows three regions which are explained. The observed dependencies are S I/I 2∝V G m with the exponents m =-1, -3, 0 with increasing values of V G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m =0 at large V G or V GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V G , m =-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance 相似文献
5.
It is shown that the influence of the drain-source field on the potential barrier height is physically equivalent to and can be replaced by a reduction in channel doping concentration according to a formula derived from the two-dimensional Poisson equation. The actual barrier height for any drain bias and channel length, on which the derived equation depends, can be calculated easily using well-known one-dimensional (long-channel) solutions. This simple but general procedure, called the voltage-doping transformation (VDT), is shown to lead to analytically calculated potential distributions in fairly good agreement with two-dimensional numerical simulation. An application of the VDT to threshold voltage (V tj) calculations also is shown. The V th model is compared with measurements taken on implanted n-MOSFETs with various channel lengths. Good agreement demonstrates the accuracy of both the VDT and the new V th model 相似文献
6.
Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V d =8 V and V g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V b), having a power-law gradient of 0.5 for V b=0 V and 0.3 for V b=-9 V. Investigation of the type of damage resulting from stressing shows that at V b=0 V, interface state generation results, while at V b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions 相似文献
7.
Nichols D. Sherwin M. Munns G. Pamulapati J. Loehr J. Singh J. Bhattacharya P. Ludowise M. 《Quantum Electronics, IEEE Journal of》1992,28(5):1239-1242
The authors have studied, both theoretically and experimentally, the effects of biaxial strain upon the performance characteristics of broad-area InP-InGaAsP-InxGa1-xAs (0.33⩽x ⩽0.73) separate confinement heterostructure multiquantum-well lasers. The theoretical calculations include the effects of strain on the bandstructure and the Auger recombination rates. A pronounced dependence of the threshold current density J th upon x is observed. The lowest measured J th is 589 A/cm2 in an 800-μm laser with x =0.68. Also, internal quantum efficiencies as high as unity and loss coefficients as low as 5.6 cm-1 have been measured for x =0.58 相似文献
8.
An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V DS over a wide range of voltages (V DS=20-100 mV). The resulting μ(V GS) curves for different V DS show no drastic mobility roll-off at V GS near V TH. This suggests that the roll-off seen in the mobility data extracted using the split C - V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering 相似文献
9.
Mode power fluctuations in semiconductors laser due to mode partition and mode hopping are discussed. The power dropout probability P e in the mode partition was measured for a wide range, 1.6×10-6⩽P e⩽1, which decreased by increasing I /I th (I and I th are the DC injection current and its threshold value respectively). The duration time t d of the power dropout expressed at t d=3.7×10 48 exp[-118 (I /I th)] for 1.065⩽I /I th⩽1.104. Power fluctuations exhibited specific characteristics around the threshold, which were similar to the critical slowing down in the phase transition phenomenon. An increase in the variance of the power fluctuations was observed when the laser oscillating condition was converted from mode partition to mode hopping. The unified stochastic model based on the Fokker-Planck approach described well both mode partition and mode hopping 相似文献
10.
Scherrer D. Kruse J. Laskar J. Feng M. Wada M. Takano C. Kasahara J. 《Electron Device Letters, IEEE》1993,14(9):428-430
The low-power microwave performance of an enhancement-mode ion-implanted GaAs JFET is reported. A 0.5-μm×100-μm E-JFET with a threshold voltage of V th=0.3 V achieved a maximum DC transconductance of g m=489 mS/mm at V ds=1.5 V and I ds=18 mA. Operating at 0.5 mW of power with V ds=0.5 V and I ds =1 mA, the best device on a 3-in wafer achieved a noise figure of 0.8 dB with an associated gain of 9.6 dB measured at 4 GHz. Across a 3-in wafer the average noise figure was F min=1.2 dB and the average associated gain was G a=9.8 dB for 15 devices measured. These results demonstrate that the E-JFET is an excellent choice for low-power personal communication applications 相似文献
11.
A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I g-V g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I g- V g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I g-V g measurements 相似文献
12.
The development of incremental and decremental V T extractors based on the square-law characteristic and an n ×n 2 transistor array is described. Different implementations have been discussed and the effect of nonidealities such as mobility reduction, channel-length modulation, mismatch, and body effect has been analyzed. Besides automatic V T extraction, parameter K of an MOS transistor can also be extracted automatically using the V T extractor, without any need of calculation and delay, and the extracted V T and K are, respectively, in voltage and current. Experimental results are presented and indicate that the differences between extracted values using the V T extractor and the most popular numerical method are as small as 0.15% and 0.064%. Additional applications, such as in level shifting, temperature compensation, and temperature measurement, where the V T extractor can be used either as a PTAT sensor or as a centigrade sensor, are presented 相似文献
13.
The effects of traps in GaAs MESFETs are studied using a pulsed gate measurement system. The devices are pulsed into the active region for a short period (typically 1 μs) and are held in the cutoff region for the rest of a 1-ms period. While the devices are on, the drain current is sampled and a series of pulsed gate I -V curves are obtained. The drain current obtained under the pulsed gate conditions for a given V GS and V DS gives a better representation of the instantaneous current for a corresponding V gs and V ds in the microwave cycle because of the effects of traps. The static and pulsed gate curves were used in a nonlinear time-domain model to predict harmonic current. The results showed that analysis using pulsed gate curves yielded better predictions of harmonic distortion than analysis based on conventional state I -V curves under large-signal conditions 相似文献
14.
Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V d=5.5 V and gate voltage V g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG m and threshold voltage shift ΔV t, do not occur at the same V g. As well, ΔK t is very small for the V g <V d stress regime, becomes significant at V g≈V d, and then increases rapidly with increasing V g, whereas ΔG m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress 相似文献
15.
Okumura Y. Shirahata M. Hachisuka A. Okudaira T. Arima H. Matsukawa T. 《Electron Devices, IEEE Transactions on》1992,39(11):2541-2552
The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V th lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V th lowering at 0.4-μm gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4-μm gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4-μm gate length 相似文献
16.
Laskar J. Ketterson A.A. Baillargeon J.N. Brock T. Adesida I. Cheng K.Y. Kolodzey J. 《Electron Device Letters, IEEE》1989,10(12):528-530
The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V ds>2.5 V and V gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V gs<0 V resulting in f max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V gs >0 V and V ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions 相似文献
17.
N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V t shift due to irradiation of the hot-electron stressed (stressing with V d=V g=6.5 V) device was less than that of the unstressed device 相似文献
18.
Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I C=15 mA, f T was 59 GHz at V CE=1.8 V, and f max was 69 GHz at V CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V CE of 3.8 V was applied for I C=7.5 mA in the S -parameter measurements to give an f T of 39 GHz and an f max of 52 GHz 相似文献
19.
It is proposed that a laser diode used as a transmitter in the transmission mode be used as a low bias current preamplifier in the receiving mode for time compression multiplexing transmission. By adopting the low bias current approach, the preamplifier is wavelength and polarization independent. The maximum bias current is determined to be about 0.5 I th (I th=threshold current) by experiments. A transmission experiment at 3.5 Mb/s reveals that about 4 dB of improvement in receiver sensitivity can be obtained by using a laser preamplifier at I =0.54 I th when compared to an unbiased laser. The receiver sensitivity of the proposed configuration (laser amplifier at low bias current and photodiode) is estimated by considering the laser preamplifier noise and circuit noise. The laser preamplifier noise is calculated by treating the laser as a traveling wave amplifier with highly reflecting facets 相似文献
20.
Chen Ih-Chin Choi Jeong Yeol Hu Chenming 《Electron Devices, IEEE Transactions on》1988,35(12):2253-2258
The correlation between channel hot-carrier stressing and gate-oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate-oxide integrity even when other parameters (e.g., ΔV T and ΔI D) have become intolerably degraded. In the extreme cases of stressing at V G≈V T with measurable hole injection current, however, the oxide charge to breakdown decreases linearly with the amount of hole fluence injected during the channel hot-hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an ESD (electrostatic discharge) failure mechanism 相似文献