Influence of surface roughness on a change in the growth mode from two-dimensional to three-dimensional for strained SiGe heterostructures

The influence of the surface microroughness on the critical thickness for the two-dimensional growth of strained SiGe structures on Si(001) and Ge(001) substrates is investigated. A decrease in the critical thickness for the two-dimensional growth of Ge films with increasing number of lattice periods or a decrease in the thickness of Si spacer layers is found for Ge/Si lattices grown on Si(001) substrates. This change is related to an increase in the surface roughness with the accumulation of elastic energy in compressed structures. A comparative study of the growth of SiGe structures on Si(001) and Ge(001) substrates shows that the critical thickness for the two-dimensional growth of tensile-strained layers is much larger than for compressed layers in a wide range of SiGe-layer compositions at an identical (in magnitude) lattice mismatch between the film and substrate.     

Self-assembled Ge/Si dots for faster field-effect transistors

Self-assembled and coherently strained germanium nanostructured dots are grown on prepatterned Si substrates along ordered lines. These precisely aligned nanocrystals are proposed to make up the central unit of a dot-based field-effect transistor (DotFET). The strain-induced band edge splitting and the inherently smaller effective masses of charge carriers in Ge/Si dots promise faster transistors than are possible for conventional pure Si devices. Thick relaxed buffer layers-mandatory for any existing high-speed SiGe field-effect devices-are no longer required. The DotFET is straight-forward, defect-free, and fully compatible with current complementary metal-oxide-semiconductor (CMOS) technology     

薄虚拟SiGe衬底上的应变Si pMOSFETs

成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT-Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe衬底的应变弛豫度为85%,表面平均粗糙度仅为1.02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.     

A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate

A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure, a 0.8-μm Si_0.1 Ge_0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si_0.1Ge_0.9 layer. A 0.8-μm Si_0.05Ge_0.95 layer and a 1-μm top Ge layer were subsequently grown. The strained Si_0.05Ge_0.95/Si_0.1Ge_0.9 and Ge/Si_0.05Ge_0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1–3-μm GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600°C. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 μm (2.6-μm SiGe-buffer structure +2.5-μm GaAs layer).     

Raman谱研究不同缓冲层结构对Si_(1-x)Ge_x应力弛豫的影响

应用 Raman散射谱研究超高真空化学气相淀积 ( UHV/CVD)生长的不同结构缓冲层对恒定组分上表层 Si1- x Gex 层应力弛豫的影响 .Raman散射的峰位不仅与 Ge组分有关 ,而且与其中的应力状态有关 .在完全应变和完全弛豫的情况下 ,Si1- x Gex 层中的 Si- Si振动模式相对于衬底的偏移都与 Ge组分成线性关系 .根据实测的 Raman峰位 ,估算了应力弛豫 .结果表明 :对组分渐变缓冲层结构而言 ,超晶格缓冲层中界面间应力更大 ,把位错弯曲成一个封闭的环 ,既减少了表面位错密度 ,很大程度上又释放了应力     

Time-resolved photoluminescence from self-assembled Ge(Si) islands in multilayer SiGe/Si and SiGe/SOI structures

The results of a study of the spectral and temporal characteristics of the photoluminescence (PL) from multilayer structures with self-assembled Ge(Si) islands grown on silicon and “silicon-on-insulator” substrates in relation to temperature and the excitation-light wavelength are presented. A substantial increase in island-related PL intensity is observed for structures with Ge(Si) islands grown on silicon substrates upon an increase in temperature from 4 to 70 K. This increase is due to the diffusion of nonequilibrium carriers from the silicon substrate into the active layer with the islands. In this case, a slow component with a characteristic time of ～100 ns appears in the PL rise kinetics. At the same time, no slow component in the PL rise kinetics and no rise in the PL intensity with increasing temperature are observed for structures grown on “silicon-on-insulator” substrates, in which the active layer with the islands is insulated from the silicon substrate. It is found that absorption of the excitation light in the islands and SiGe wetting layers mainly contributes to the excitation of the PL signal from the islands under sub-bandgap optical pump conditions.     

Si1-xGex/Si应变材料的生长及热稳定性研究

利用分子束外延（MBE）技术生长了Ge组份为0.1-0.46的Si1-xGex外延层。X射线衍射线测试表明，SiGe/Si异质结材料具有良好的结晶质量和陡峭界面，其它参数与可准确控制。通过X射线双晶衍射摆曲线方法，研究了经700℃、800℃和900℃退火后应变SiGe/Si异质结材料的热稳定性。结果表明，随着退火温度的提高，应变层垂直应变逐渐减小，并发生了应变弛豫，导致晶体质量退化；且Ge组分越小，Si1-xGex应变结构的热稳定性越好；室温下长时间存放的应变材料性能稳定。     

Transition from the two- to three-dimensional growth of Ge films upon deposition onto relaxed SiGe/Si(001) buffer layers

The critical thickness of the two-dimensional growth of Ge on relaxed SiGe/Si(001) buffer layers different in Ge content is studied in relation to the parameters of the layers. It is shown that the critical thickness of the two-dimensional growth of Ge on SiGe buffer layers depends on the lattice mismatch between the film and the substrate and, in addition, is heavily influenced by Ge segregation during SiGe-layer growth and by variations in the growth-surface roughness upon the deposition of strained (stretched) Si layers. It is found that the critical thickness of the two-dimensional growth of Ge directly onto SiGe buffer layers with a Ge content of x = 11–36% is smaller than that in the case of deposition onto a Si (001) substrate. The experimentally detected increase in the critical thickness of the two-dimensional growth of Ge with increasing thickness of the strained (stretched) Si layer predeposited onto the buffer layer is attributed to a decrease in the growth-surface roughness and in the amount of Ge located on the surface as a result of segregation.     

Special features of the formation of Ge(Si) islands on the relaxed Si1−xGex/Si(001) buffer layers

The results of studying the growth of self-assembled Ge(Si) islands on relaxed Si_1?xGe_x/Si(001) buffer layers (x≈25%), with a low surface roughness are reported. It is shown that the growth of self-assembled islands on the buffer SiGe layers is qualitatively similar to the growth of islands on the Si (001) surface. It is found that a variation in the surface morphology (the transition from dome-to hut-shaped islands) in the case of island growth on the relaxed SiGe buffer layers occurs at a higher temperature than for the Ge(Si)/Si(001) islands. This effect can be caused by both a lesser mismatch between the crystal lattices of an island and the buffer layer and a somewhat higher surface density of islands, when they are grown on an SiGe buffer layer.     

Studies on the growth of CdTe on Si using ge interfacial layer in an organometallic vapor phase epitaxial system

Epitaxial CdTe layers were grown using organometallic vapor phase epitaxy on Si substrates with a Ge buffer layer. Ge layer was grown in the same reactor using germane gas and the reaction of germane gas with the native Si surface is studied in detail at low temperature. It is shown that germane gas can be used to “clean” the Si surface oxide prior to CdTe growth by first reducing the thin native oxide that may be present on Si. When Ge layer was grown on Si using germane gas, an induction period was observed before the continuous layer of Ge growth starts. This induction period is a function of the thickness of the native oxide present on Si and possible reasons for this behavior are outlined. Secondary ion mass spectrometry (SIMS) data show negligible outdiffusion and cross contamination of Ge in CdTe.     

Thermally Processed High-Mobility MOS Thin-Film Transistors on Transferable Single-Crystal Elastically Strain-Sharing Si/SiGe/Si Nanomembranes

Demonstration of high-performance MOS thin-film transistors (TFTs) on elastically strain-sharing single-crystal Si/SiGe/Si nanomembranes (SiNMs) that are transferred to foreign substrates is reported. The transferable SiNMs are realized by first growing pseudomorphic SiGe and Si layers on silicon-on-insulator (SOI) substrates, and then, selectively removing the buried oxide (BOX) layer from the SOI. Before the release, only the SiGe layer is compressively strained. Upon release, part of the compressive strain in the SiGe layer is transferred to the thin Si layers, and the Si layers, thus, become tensile strained. Both the initial compressive strain state in the SiGe layer and the final strain sharing state between the SiGe and the Si layers are verified with X-ray diffraction measurements. The TFTs are fabricated employing the conventional high-temperature MOS process on the strain-shared SiNMs that are transferred to an oxidized Si substrate. The transferred strained-sharing SiNMs show outstanding thermal stability and can withstand the high-temperature TFT process on the new host substrate. The strained-channel TFTs fabricated on the new host substrate show high current drive capability and an average electron effective mobility of 270 cm²/V ldr s. The results suggest that transferable and thermally stable single-crystal elastically strain- sharing SiNMs can serve as excellent active material for high-speed device application with a simple and scalable transfer method. The demonstration of MOS TFTs on the transferable nanomembranes may create the opportunity for future high-speed Si CMOS heterogeneous integration on any substrate.     

Tensile-Strained Germanium CMOS Integration on Silicon

Monolithic integration of tensile-strained Si/ Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness ~14 Aring) HfO₂ gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ~0.67% and exhibits a peak hole mobility of 250 cm²/V ldr s which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk.     

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.     

Growth and characterization of GaAs films deposited on Ge/Si composite substrates by metalorganic chemical vapor deposition

We report the results of studies which have been made on heteroepitaxial layers of GaAs and AlGaAs grown by metalorganic chemical vapor deposition on composite substrates that consist of four different types of heteroepitaxial layered structures of Ge and Ge-Si grown by molecular beam epitaxy on (100)-oriented Si substrates. It is found that of the four structures studied, the preferred composite substrate is a single layer of Ge ∼1 μm thick grown directly on a Si buffer layer. The double-crystal X-ray rocking curves of 2 μm thick GaAs films grown on such substrates have FWHM values as small as 168 arc sec. Transmission electron micrographs of these Ge/Si composite substrates has shown that the number of dislocations in the Ge heteroepitaxial layer can be greatly reduced by an anneal at about 750° C for 30 min which is simultaneously carried out during the growth of the GaAs layer. The quality of the GaAs layers grown on these composite substrates can be greatly improved by the use of a five-period GaAs-GaAsP strained-layer superlattice (SLS). Using the results of these studies, low-threshold optically pumped AlGaAs-GaAs DH laser structures have been grown by MOCVD on MBE Ge/Si composite substrates.     

采用低温Si技术的Si/SiGe异质结P-MOSFET

针对S i/S iG e p-M O SFET的虚拟S iG e衬底厚度较大(大于1μm)的问题,采用低温S i技术在S i缓冲层和虚拟S iG e衬底之间M BE生长低温-S i层。S iG e层应力通过低温-S i层释放,达到应变弛豫。XRD和AFM测试表明,S i0.8G e0.2层厚度可减薄至300 nm,其弛豫度大于85%,表面平均粗糙度仅为1.02 nm。试制出应变S i/S iG e p-M O SFET器件,最大空穴迁移率达到112 cm2/V s,其性能略优于目前多采用1μm厚虚拟S iG e衬底的器件。     

Structural characterization of thick, high-quality epitaxial Ge on Si substrates grown by low-energy plasma-enhanced chemical vapor deposition

In this paper, we report on the growth of epitaxial Ge on a Si substrate by means of low-energy plasma-enhanced chemical vapor deposition (LEPECVD). A Si_1?xGe_x graded buffer layer is used between the silicon substrate and the epitaxial Ge layer to reduce the threading dislocation density resulting from the lattice mismatch between Si and Ge. An advantage of the LEPECVD technique is the high growth rate achievable (on the order of 40 Å/sec), allowing thick SiGe graded buffer layers to be grown faster than by other epitaxial techniques and thereby increasing throughput in order to make such structures more manufacturable. We have achieved relaxed Ge on a silicon substrate with a threading dislocation density of 1 × 10⁵ cm^?2, which is 4?10x lower than previously reported results.     

Photoluminescence line width of self-assembled Ge(Si) islands arranged between strained Si layers

The effect of variations in the strained Si layer thicknesses, measurement temperature, and optical excitation power on the width of the photoluminescence line produced by self-assembled Ge(Si) nanoislands, which are grown on relaxed SiGe/Si(001) buffer layers and arranged between strained Si layers, is studied. It is shown that the width of the photoluminescence line related to the Ge(Si) islands can be decreased or increased by varying the thickness of strained Si layers lying above and under the islands. A decrease in the width of the photoluminescence line of the Ge(Si) islands to widths comparable with the width of the photoluminescence line of quantum dot (QD) structures based on direct-gap InAs/GaAs semiconductors is attained with consideration of diffusive smearing of the strained Si layer lying above the islands.     

超高真空化学气相生长用于应变硅的高质量SiGe缓冲层

采用UHV/CVD技术,以多层SiGe/Si结构作为缓冲层来生长应变弛豫SiGe虚衬底,并在此基础上生长出了具有张应力的Si层.利用高分辨X射线、二次离子质谱仪和原子力显微镜分别对薄膜的晶体质量、厚度以及平整度进行了分析.结果表明,通过这种方法制备的SiGe虚衬底,不仅可以有效提高外延层中Ge含量,以达到器件设计需要,而且保证很好的晶体质量和平整的表面.Schimmel液腐蚀后观察到的位错密度只有1×106cm-2.     

Growth of a Ge Layer on a Si/SiO2/Si(100) Structure by the Hot Wire Chemical Vapor Deposition

Semiconductors - Ge/Si layers are formed on Si/SiO2/Si(100) substrates and are investigated for different growth temperatures. The Si layer is grown by molecular-beam epitaxy, while the Ge layer is...     

Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si_0.82Ge_0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.