A symmetrical 6-GHz fully integrated cascode coupling CMOS LC quadrature VCO

A fully symmetrical integrated quadrature LC oscillator with a wide tuning range of 1.2GHz is presented. The quadrature voltage-controlled oscillator (QVCO) is implemented using a symmetrical coupling method which has been used to produce the large tuning range with a low control voltage and to achieve good phase noise performance in 0.18/spl mu/m complementary metal oxide semiconductor technology. The measured phase noise at 1MHz offset from the center frequency (5.5GHz) is -115 dBc/Hz. The QVCO draws 3.2mA from a 1.8V supply. The equivalent phase error between I and Q signal was at most 0.5/spl deg/.     

A wide-range 22-GHz LC-based CMOS voltage-controlled oscillator

This work presents a novel voltage-controlled oscillator (VCO) design and simulations that combine a varactor bank with a transformer in the LC tank to achieve a high-frequency range. While the varactor bank is responsible for changing the capacitance in the LC tank, the transformer acts as a means to change the value of the inductance, hence allowing tune-ability in the two main components of the VCO. A control mechanism utilises a mixed-mode circuit consisting of comparators and a state machine. It allows efficient tuning of the VCO by controlling the capacitance and transformer in the LC tank. The VCO has a 10.75–22.43 GHz frequency range and the VCO gain, K_VCO, is kept at a low value ranging from 98.6 to 175.7 MHz/V. The simulated phase noise is ?111 dBc/Hz at 1 MHz offset from the 10.75 GHz oscillation frequency. The circuit is designed and simulated in 28 nm CMOS technology and uses a 1 V supply drawing a typical power of 14.74 mW.     

A 22-GHz push-push CMOS oscillator using micromachined inductors

This letter presents a low phase noise 0.35-/spl mu/m CMOS push-push oscillator utilizing micromachined inductors. This oscillator results in an improvement in phase noise compared with the previously published Si-based voltage-controlled oscillators (VCOs) around 20GHz. With the high-Q inductors introduced by the micromachined structure, the oscillator achieves an oscillating frequency of 22.2GHz while exhibiting an output power of -7.5dBm with a phase noise of -110.1dBc/Hz at 1-MHz offset. This work also demonstrates the highest operating frequency among previously published Si-based VCOs using micromachined structures.     

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.     

100-GHz high-gain InP MMIC cascode amplifier

A high-gain InP monolithic millimeter-wave integrated circuit (MMIC) cascode amplifier has been developed which has 8.0 dB of average gain from 75 to 100 GHz when biased for maximum bandwidth, and more than 12 dB of gain at 80 GHz at the maximum-gain bias point, representing the highest gains reported to date, obtained from MMICs at W band (75-100 GHz). Lattice-matched InGaAs-InAlAs high-electron-mobility-transistors (HEMTs) with 0.1-μm gates were the active devices. A coplanar waveguide (CPW) was the transmission medium for this MMIC with an overall chip dimension of 600×500 μm     

Self-biasing of folded cascode CMOS op-amps

In cascode CMOS op-amps a large number transistors are biased using independent standard bias circuits. This results in numerous drawbacks, namely, an area and power overhead, and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no bias voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded cascode op-amps. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op-amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.     

1-V power supply CMOS cascode amplifier

We design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69-dB DC gain, a 2-MHz bandwidth, and compatible input- and output voltage levels at a 1-V power supply. This is done by a novel, current driven bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique     

A low-power up-conversion CMOS mixer for 22-29-GHz ultra-wideband applications

A double-balanced, low-power, and low-voltage dual-gate up-conversion mixer working at K-band is designed and fabricated in the UMC 130-nm logic CMOS process. The mixer achieves a 3-dB conversion-gain bandwidth of 1.8 GHz at the input IF port and a 3-dB conversion-gain bandwidth of 10 GHz at the output RF port. The mixer achieves an output referred 1-dB compression point as high as -5.8 dBm and an output referred third-order intercept point as high as 5.8 dBm, while consuming 8.0 mW from a 1.2-V supply. This study demonstrates that the implementation of low-power mixers operating in the 22-29-GHz band for ultra-wideband automotive radar applications is possible in low-cost and low-voltage logic CMOS technology.     

2-GHz CMOS射频低噪声放大器的设计与测试

本文采用CMOS工艺,针对无线通信系统前端(Front-end)的低噪声放大器进行了分析、设计、仿真和测试.测试结果表明,该放大器工作在2.04-GHz的中心频率上,3dB带宽约为110MHz,功率增益为22dB,NF小于3.3dB.测试结果与仿真结果能够很好地吻合.     

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor f_T/f_MAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P _1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP ₃ of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm² and 0.35times0.40 mm², respectively     

一种5 GHz WLAN CMOS正交调制器和上变频器的设计

介绍了应用于WLAN IEEE 802.11a的正交调制器和上变频器的设计,给出了详尽的优化方法。正交调制器在传统Gilbert单元的基础上,采用负反馈跨导放大器来提高线性度;上变频器采用RLC谐振网络作Gilbert单元负载来提高增益,增加电压输出摆幅。电路采用TSMC 0.18μm 6层金属混合信号/射频CMOS工艺实现。在1.8 V电源电压下,静态电流为30 mA。测试结果表明,在谐振频率点的1 dB压缩点P1-dB为-8 dBm,电压增益为-2.4 dB,本振泄漏小于-50 dBm。     

适合于多吉赫兹应用的0.5 V CMOS cascode低噪声放大器设计

本文介绍了适用于低功耗无线通信的0.5 V 多吉赫兹CMOS cascode 低噪声放大器设计。通过对传统cascode结构进行直流分离,去除了因堆积MOS管导致的工作电压限制。同时,采用正向体偏置技术,cascode结构低噪声放大器能工作在0.5 V供电电压。文章研究了电路设计细节和射频性能。为验证研究结果,采用台积电0.18微米射频工艺的0.5 V 5.4吉赫兹低噪声放大器被设计,制造出来并进行了测量。测量结果表明,该低噪声放大器在0.5 V工作电压下工作电流为5毫安,其增益为9.1分贝,噪声系数为3分贝,输入三阶交调点为-3.5 分贝毫瓦。通过和那些已发表的cascode低噪声放大器比较,本文的低噪声放大器具有工作电压低,功耗低而射频性能相当的特点。     

Design Theory and Performance of 1-GHz CMOS Downconversion and Upconversion Mixers

A CMOS mixer topology capable of both downconversion and upconversion mixing for use in integrated wireless transceivers is presented. The mixing is based on two cross-coupled differential pairs as commutators with two source-followers as current modulators. Independence of the input and output bandwidths allows this topology to be optimized separately for either downconversion or upconversion mixer. The prototypes of both upconversion and downconversion mixers, optimized for linearity and realized in 0.8 m CMOS technology, have been demonstrated to fully operate at 1 GHz with good linearity and low power consumption. In addition, another mixer, optimized for noise figure and realized in 0.5 m CMOS technology, has been designed to achieve a NF of around 12 dB.     

Design of 60- and 77-GHz Narrow-Bandpass Filters in CMOS Technology

This paper investigates the design and implementation of millimeter-wave narrow-bandpass filters in a standard 0.18- $mu$m CMOS technology. Filters with a measured 10% 3-dB bandwidth at 60 and 77 GHz are realized in a thin-film microstrip structure by using the lowest metallization layer as a ground plane. The impact of dissipation losses of the filters is also examined. It is found that the metallization losses in the coupled-line filter as well as the ground plane are the main reasons for the insertion loss.      

Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-μm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 14.5 dB, input P1dB of ?17.5 dBm, and input IP3 of ?13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 17 dB, input P1dB of ?22 dBm, and input IP3 of ?14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA’s targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure     

A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop

A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-/spl mu/m foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve high-speed operation. The maximum operating frequency of the prescaler is 14 GHz at V/sub DD/=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I/sub vco/=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I/sub vco/=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes /spl sim/31 mA at V/sub DD/=1.8 V.     

Design and frequency/phase-noise analysis of a 10-GHz CMOS ring oscillator with coarse and fine frequency tuning

A 10-GHz CMOS ring oscillator that employs a multi-pass technique for boosting its frequency is proposed in this paper. The proposed circuit allows the tuning gain to be lowered by deploying the coarse/fine frequency tuning whilst maintaining wide frequency coverage. The small signal model of the proposed delay stage and the circuit operation are discussed in this paper. The time-variant analysis presented permits accurate prediction of the frequency tuning characteristic and the results have been verified by simulation. The phase noise analysis is also discussed in detail to provide better insight to the noise that is contributed by each transistor. The calculated results agreed well with that of the simulations. Hai Qi Liu was born in Jiangsu, China, in 1979. He received the B.S. and M.Sc. degrees, both in electrical engineering from the Tianjin University, Tianjin, China, in 2000, and Tongji University, Shanghai, China, in 2003, respectively. He is currently working toward the Ph.D. degree at the Nanyang Technological University, Singapore. His research focuses mainly on the design of fully integrated oscillators and Phase-Locked Loops for optical communication applications. His research interests also include RF frequency synthesizers and RF front-end designs for wireless applications. Wang Ling Goh obtained both her B.Eng and Ph.D. degrees from the department of Electrical and Electronic Engineering at the Queen’s University of Belfast (QUB) in United Kingdom. When working on her Ph.D., she was also engaged as a research associate at the Northern Ireland Semiconductor Research Centre (NISRC) at QUB. Dr Goh joined the School of Electrical and Electronic Engineering at the Nanyang Technological University (NTU) in Singapore as a lecturer in January 1996. She is now an Associate Professor in the Division of Circuits and Systems, School of Electrical & Electronic Engineering. Dr Goh has to-date co-authored 1 book, filed 13 patents (granted), and published about 60 research papers in international conferences and journals. Her research interests are in areas of silicon device processing technologies as well as digital and mixed-signal IC designs. Liter Siek received the B.A.Sc. degree from University of Ottawa, Ontario, Canada; the M.Eng.Sc. from University of New South Wales, Sydney, Australia; and the Ph.D. from Nanyang Technological University, Singapore. From 1981 to 1983 he was employed in several companies in the area of automation and control. From 1983 to 1985, he was with SGS, currently known as ST Microelectronics situated in Castelletto, Milan, Italy, where he worked in the central R&D Laboratories for Linear IC. From 1985 to 1987, he was with the same company situated in Singapore’s Asia Pacific Design Center. Since October 1988, he has been with Nanyang Technological University. His research interests are in the design of bipolar, CMOS and BiCMOS analog/mixed signal ICs. In addition, he has authored and co-authored 53 international journal/conference technical papers.     

A 60-GHz CMOS receiver front-end

The unlicensed band around 60 GHz can be utilized for wireless communications at data rates of several gigabits per second. This paper describes a receiver front-end that incorporates a folded microstrip geometry to create resonance at 60 GHz in a common-gate LNA and active mixers. Realized in 0.13-/spl mu/m CMOS technology, the receiver front-end provides a voltage gain of 28 dB with a noise figure of 12.5 dB while consuming 9 mW from a 1.2-V supply.     

The Design of Low LO-Power 60-GHz CMOS Quadrature-Balanced Self-Switching Current-Mode Mixer

This letter describes the analysis and measurement of a complementary metal-oxide semiconductor (CMOS) quadrature-balanced current-mode mixer with a 90^deg branch-line hybrid coupler and self-switching current-mode devices. The proposed mixer, using 0.13 mum 1P8M CMOS technology, can downconvert a 60 GHz RF signal to a 2 GHz intermediate frequency (IF) signal, with a local-oscillator power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1 dB and an input-referred 1 dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve -37 dB while using 3 mA from a supply voltage of 1.2 V.     

The utility of the composite cascode in analog CMOS design

This work demonstrates the utility of the composite cascode stage by considering its use (1) as a high-gain amplifying stage; (2) as a high-impedance load for an amplifying stage; and (3) as a low-impedance, high-frequency summing circuit. A simulation of the summing circuit using 0.18?µm channel lengths leads to a rise time of less than 30?ps and good linearity. When used as a high-gain amplifier, both devices of the active cascode stage must be biased into the active region. In the summing circuit, one device is biased into the triode region whereas the second device must operate in the active region. Guidelines for achieving proper bias with a single bias source are provided in this work.