A Single Phase Voltage Regulator Module (VRM) With Stepping Inductance for Fast Transient Response

A single-phase fast transient converter topology with stepping inductance is proposed. The stepping inductance method is implemented by replacing the conventional inductor in a buck converter by two inductors connecting in series. One has large inductance and the other has small inductance. The inductor with small inductance will take over the output inductor during transient load change and speed up dynamic response. In steady state, the large inductance takes over and keeps a substantially small ripple current and minimizes root mean square loss. It is a low cost method applicable to converters with an output inductor. A hardware prototype of a 1.5-V dc-dc buck converter put under a 100-A transient load change has been experimented upon to demonstrate the merit of this approach. It also serves as a voltage regulator module and powers up a modern PC computer system     

Design issues for monolithic DC-DC converters

This paper presents various ideas for integrating different components of dc-dc converter on to a silicon chip. These converters are intended to process power levels up to 0.5W. Techniques for integrating capacitors and design issues for MOS transistors are discussed. The most complicated design issue involves inductors. Expressions for trace resistance and inductance estimation of on-chip planar spiral inductor on top metal layer of CMOS process are compared. These inductors have high series resistance due to low metal trace thickness, capacitive coupling with substrate and other metal traces, and eddy current loss. As an alternative, a CMOS compatible three-dimensional (3-D) surface micromachining technology known as plastic deformation magnetic assembly (PDMA) is used to fabricate high quality inductors with small footprints. Experimental results from a monolithic buck converter using this PDMA inductor are presented. A major conclusion of this work is that the 3-D "post-process" technology is more viable than traditional integrated circuit assembly methods for realizing of micro-power converters.     

Performance improvements of interleaving VRMs with couplinginductors

The multichannel interleaving buck converter with small inductance has proved to be suitable for voltage regulator modules (VRMs) with low voltages, high currents, and fast transients. Integrated magnetic components are used to reduce the size of the converter and improve efficiency. However, the structure of the integrated magnetic requires precise adjustment and is not mechanical stable. This paper proposes integrated coupling inductors between the channels to solve these problems. With the proper design, coupling inductors can improve both the steady-state and dynamic performances of VRMs with easier manufacturing     

Voltage Regulator Optimization Using Multiwinding Coupled Inductors and Extended Duty Ratio Mechanisms

This paper examines design optimization of voltage regulators (VRs) for microprocessor applications. Optimality of competing VR topologies, such as conventional (Conv) buck, coupled inductor, and extended duty ratio converters, is examined using efficiency norms and a new cost-per-watt metric to compare the amount of output capacitance (which is strongly correlated to the VR cost) to the efficiency. Coupled inductors provide a higher steady-state inductance than transient inductance. Lower transient inductance allows for smaller output capacitance. However, lower output capacitance requires a higher switching frequency and thus yields greater switching losses and lower efficiency. Extended duty ratio mechanisms reduce the switching voltage, and hence, reduce switching losses and increase efficiency. Experimental data are provided that the coupled inductor extended duty ratio converter has the same average efficiency, has higher light-load efficiency, and uses one-third of the output capacitance as the Conv multiphase buck converter. Hence, the combination of multiwinding coupled inductors and extended duty ratio mechanisms is shown to be the optimal VR configuration. The optimality concepts contributed in this paper resolve the ambiguity between VR cost and efficiency, and are essential for selecting the best solution among several competing VR designs.      

A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18 μm SiGe Process

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.     

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.     

A zero-voltage-switched three-phase interleaved buck converter

This paper proposes a three-phase interleaved buck converter which is composed of three identical paralleled buck converters. The proposed solution has three shunt inductors connected between each other of three basic buck conversion units. With the help of the shunt inductors, the MOSFET parasitic capacitances will resonate to achieve zero-voltage-switching. Furthermore, the decreasing rate of the current through the free-wheeling diodes is limited, and therefore, their reverse-recovery losses can be minimised. The active power switches are controlled by interleaved pulse-width modulation signals to reduce the input and output current ripples. Therefore, the filtering capacitances on the input and output sides can be reduced. The power efficiency is measured to be as high as 98% in experiment with a prototype circuit.     

PCB integrated inductors for low power DC/DC converter

This paper discusses the use of printed circuit board (PCB) integrated inductors for low power DC/DC buck converters. Coreless, magnetic plates and closed core structures are compared in terms of achievable inductance, power handling and efficiency in a footprint of 10 /spl times/ 10 mm/sup 2/. The magnetic layers consist of electroplated NiFe, so that the process is fully compatible with standard PCB process. Analytic and finite element method (FEM) methods are applied to predict inductor performance for typical current waveforms encountered in a buck converter. Conventional magnetic design procedures are applied to define optimum winding and core structures for typical inductor specifications. A 4.7 /spl mu/H PCB integrated inductor with dc current handling of up to 500 mA is presented. This inductor is employed in a 1.5 W buck converter using a commercial control integrated circuit (IC). The footprint of the entire converter measures 10 /spl times/ 10 mm/sup 2/ and is built on top of the integrated inductor to demonstrate the concept of integrated passives in power electronic circuits to achieve ultra flat and compact converter solutions.     

Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs

An on-chip buck converter which is implemented by stacking chips and suitable for on-chip distributed power supply systems is proposed. The operation of the converter with 3-D chip stacking is experimentally verified for the first time. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70 mA and a voltage conversion ratio of 0.7 with a switching frequency of 200 MHz and a 2 times2 mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35-mum CMOS and connected with metal bumps. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3% is also discussed.     

一种新型交错并联同相降压升压DC/DC转换器

为了有效降低电流纹波和提高转换器效率,提出一种新型交错并联同相降压升压DC/DC转换器。提出的结构通过采用输入/输出（I/O）磁耦合交错并联和阻尼网络技术,降低了开关的电压应力、内部电压振荡和I/O电流纹波,并提升了转换器的效率。采用状态空间平均法,在连续导通模式下分析了提出转换器的稳态运行,从理论上证明了其优势。样机的功率设置为360W,输出电压为36 V,模拟结果以及实验结果显示,当输出电流为6A时,转换效率最高达到96%,最大输入电流纹波百分比仅为9.4%,相较于其他类似转换器,提出的转换器具有效率较高和I/O电流纹波较低的优势。     

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.     

Inductorless DC-to-DC converter with high power density

A new type of switching-mode power supply containing no inductors or transformers is proposed. The controlled transfer of energy from a unregulated DC source to a regulated output voltage is realized through a switched-capacitor (SC) circuit. A duty-cycle control is used; the driving signals of the transistors in the SC circuit are determined by the feedback circuit. The absence of magnetic devices makes possible the realization of power converters of small size, low weight and high power density, able to be manufactured in IC technology. High efficiency, small output voltage ripple and good regulation for large changes in the input voltage and/or load values are other positive features of the new type of DC-to-DC power converter. The input-to-output voltage conversion ratio is flexible; the same converter structure can provide a large range of constant desired values of the output voltage for a given input voltage, by predetermining the steady-state conversion ratio. The frequency response shows good stability of the designed converter. The experimental results obtained by using a prototype of a step-down SC-based DC-to-DC converter confirmed the theoretical expectations and the computer simulation results.<>     

Design of 48 V Voltage regulator modules with a novel integrated magnetics

The push-pull forward topology with the current-doubler and synchronous rectifier is a suitable approach for high-input voltage regulator modules (VRMs) used to supply high-performance microprocessors. In order to improve efficiency and reduce size, this paper proposes an improved push-pull forward converter with a novel integrated magnetics. All the magnetic components including input filter inductor, step-down transformer and output filter inductors are integrated into a single EI or EE core. This topology is essentially the modified push-pull converter with the built-in input filter and the coupled-inductor current doubler rectifier. The proposed integrated magnetic structure features a simple core structure, a small leakage inductance and low winding and core losses. A design is given for a 48-V VRM with a 1.2-V and 70-A output, and its experimental results show that the proposed approach can offer a great improvement in efficiency.     

Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can be combined with the buck, buck-boost, Cuk, Zeta, Sepic converters in order to get a step-down function. When the active switch of the converter is on, the inductors in the L-switching blocks are charged in series or the capacitors in the C-switching blocks are discharged in parallel. When the active switch is off, the inductors in the L-switching blocks are discharged in parallel or the capacitors in the C-switching blocks are charged in series. The ldquostep-uprdquo C- or L-switching structures are combined with the boost, buck-boost, Cuk, Zeta, Sepic converters, to get a step-up function. The steady-state analysis of the new hybrid converters allows for determing their DC line-to-output voltage ratio. The gain formula shows that the hybrid converters are able to reduce/increase the line voltage more times than the original, classical converters. The proposed hybrid converters contain the same number of elements as the quadratic converters. Their performances (DC gain, voltage and current stresses on the active switch and diodes, currents through the inductors) are compared to those of the available quadratic converters. The superiority of the new, hybrid converters is mainly based on less energy in the magnetic field, leading to saving in the size and cost of the inductors, and less current stresses in the switching elements, leading to smaller conduction losses. Experimental results confirm the theoretical analysis.     

DC/DC变换器自适应模糊逻辑控制器设计

文章为DC/DC变换器设计了一种自适应模糊逻辑控制器（AFLC）。所提出的AFLC不需要专家系统提供决策参数和控制规则,而是使用模型数据文件来产生参数和规则,该模型数据文件包含输入输出对的整体概况。所提出的控制器使用8位微控制器来实现降压、升压和降压-升压变换器。     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.     

Family of Soft-Switching PWM Converters With Current Sharing in Switches

In this paper, a new family of soft-switching pulsewidth modulation (PWM) converters is introduced. In this family of converters, two switches operate out of phase and share the output current while providing soft-switching condition for each other. A buck converter, from this family of converters, is analyzed and its operating modes are discussed. The adoption of regular PWM control circuit to the proposed converters is presented. A prototype converter is implemented and its experimental results are illustrated.     

A New Monolithic Fast-Response Buck Converter Using Spike-Reduction Current-Sensing Circuits

A new monolithic fast-response buck converter using spike-reduction current-sensing circuits is proposed in this paper. The proposed converters are designed and implemented with TSMC 0.35-mum DPQM CMOS processes. The operation frequency can be up to 1.887 MHz. The response time is only 2 mus and compared with other references. The maximum output current is 750 mA, and the maximum power efficiency can be up to 89.1% at 2.442-W output power. The chip area is only 2.157 mm².     

A small signal coupling model for predicting the coupling between LNAs

A small signal coupling model is developed to analyze the coupling between two LNAs. The mutual inductance between the adjacent on-chip inductors is considered responsible for this coupling. A set of formulas have been derived to quantitatively predict the coupling effects. Based on our analysis, a quick estimation can be made to see which pair of inductors plays a key role in evaluating the coupling between the LNAs. Source inductors of two LNAs are placed closely while the load inductors are far apart according to the analysis. To validate the proposed theory, two 2 GHz LNAs are fabricated. The LNAs have a peak gain of 18 dB and NF of 1.4 dB. The coupling between the LNAs is -30 dB.