一种高性能多路射频交换矩阵的设计与实现

在通信信号密集、信号强度差别大的背景下,为保证多路接收系统既不饱和又不漏掉微弱的小信号,需要接收通路具有较大动态,同时还要求较低的噪声系数。针对大规模接收系统几项重要指标,如隔离度、噪声系数及动态值等,在反复设计基础上,对射频交换矩阵设备进行了仿真及试验。通过测试数据分析,各项指标达到综合权衡。多路射频全交换矩阵的技术设计方法可以获得较高接收性能。     

短波射频交换矩阵不间断故障切换系统的设计与应用

本文介绍了一套基于C#的射频矩阵灾备系统,通过软件实现两种射频矩阵的联动,并着重对射频交换矩阵故障切换原理、故障切换模式以及与其他系统协同办公模式进行了介绍。该系统自成一体,具有很高的操作灵活度,在提高使用体验度的同时,为保障短波广播安全播出提供了支持。     

一种超低插损砷化镓射频开关

报道了利用离子注入技术研制出一种用于手机的超低插损砷化镓单片射频单刀双掷开关。该产品在82 0～ 95 0 MHz下 ,插入损耗≤ 0 .4 d B,回波损耗≥ 1 9.5 d B,反向三阶交调截距点≥ 67d Bm,隔离度≥ 1 5 .5 d B,控制电压为 (0 ,+4 .75 V)     

一种L～E波段的混合型射频MEMS单刀双掷开关设计

针对传统RF MEMS单刀双掷(SPDT)开关应用存在频段低、插入损耗高、隔离度低等问题,设计了一种混合型SPDT开关,通过在一条通路上设置接触式开关和电容式开关,实现了在L～E频段下的低插入损耗和高隔离度。通过设计蛇形上电极结构,降低了上电极的弹性系数,进而降低开关上电极下拉所需的驱动电压。采用HFSS仿真软件对混合型SPDT开关的射频性能参数进行了优化,并利用COMSOL对开关的蛇形上电极进行应力-位移分析。仿真结果表明,在DC～90 GHz的频段下,SPDT开关的插入损耗小于1.5 dB@90 GHz,隔离度大于52 dB@67 GHz、29 dB@90 GHz。此开关适用于无线通信系统、雷达系统和仪器测量系统等对工作频段要求高的领域内。     

RF MEMS单刀四掷矩阵开关的研究

介绍了一个RF MEMS单刀四掷矩阵开关的设计，用四个串联式、电阻接触型、悬臂梁RF MEMS开关制作在微带电路板上完成。在频带1～5GHz内，单刀四掷矩阵开关的插入损耗〈0．8dB，开关隔离度〉38dB，驻波系数〈1．2。悬臂梁开关的激励电压为直流电压35～45V。     

改进K型单刀四掷射频MEMS开关

针对射频器件小型化以及5G通信发展的需求,设计了一款射频微机电系统（RF-MEMS）单刀四掷开关。该开关由一个改进型K型功分器和六个单刀单掷开关级联构成,并基于硅基MEMS工艺进行制造。其中,改进型K型功分器由多个Y型功分器串并联构成。改进的开关各端口具有插入损耗小和隔离度高的特点。最终流片的测试结果显示：该单刀四掷MEMS开关的插入损耗优于2.8 dB,隔离度优于29 dB。     

一种单刀双掷高速模拟开关的研制

介绍了一种单刀双掷高速模拟开关;描述了电路工作原理、线路设计、版图设计及可靠性设计。该高速模拟开关具有速度快、功耗低、隔离度高、关断漏电流小等特点。其内部电路设计有控制输入级、电平转换级、高速模拟开关管及静电保护电路。该电路可广泛应用于雷达接收机和发射机、通信系统和数据采集系统,以及通用模拟开关等领域。     

用于通信系统测量的射频开关矩阵

为了解决通信系统测量时需要频繁更换测量仪器的问题,分析通信系统的测量类别、接口要求及常用通信测量仪器的特性、输入输出方式、频率使用范围、功率限制等指标。在此基础上设计了用于通信系统测量的射频开关矩阵,采用高性能程控开关切换测量仪器,在信号通路上增加衰减器控制信号功率,将待测通信系统和多种通信测量仪器有机组合,构成一个完整的测量系统。射频开关矩阵可以进行灵活连接,实现多入多出。所有测量仪器都使用射频开关矩阵选择,测量仪器受限于实验空间的情况得到极大改善。测量时不需手动更换待测模块和测量仪器,只需在射频开关矩阵的操作界面进行选择,即可方便地在仪器常开状态下进行测量且不会对仪器产生影响。     

宽带单刀多掷PIN开关的设计

介绍了微波PIN开关的电磁结构模型的建立及计算机仿真，讨论了宽带单刀多掷开关的设计要点。采用该方法成功设计了1—18GHz吸收式单刀五掷开关，其插损≤3．5dB．驻波≤2．2，隔离度≥60dB。     

一种2.4 GHz CMOS射频前端电路

基于0.18 μm CMOS工艺,设计了一种面向低速率低功耗应用的2.4 GHz射频前端电路,包含2个单刀双掷开关、1个功率放大器和1个低噪声放大器。采用栅衬浮动电压偏置技术对传统单刀双掷开关进行了改进,以提高其线性度;功率放大器采用两级放大结构,对全集成的低噪声放大器进行了噪声优化;集成了输入输出匹配网络,采用了到地电感,以提高输入输出端的ESD性能。在接收模式时,电路的静态电流为10.7 mA,增益为11.7 dB,IIP3为2.1 dBm,噪声系数为3.4 dB。在发射模式时,电路的静态电流为17.4 mA,功率增益为17.7 dB,输出P1dB为20 dBm,饱和功率为21.4 dBm,最大PAE为23.8%,在输出功率为20 dBm时的频谱满足802.15.4协议要求。     

A circuit for high-speed time switching

A method of time switching for time-division communication systems is introduced. A compact shift register-based circuit is used for this purpose in order to achieve high-speed switching     

Optical TDM sorting networks for high-speed switching

The general time-space-time switching problem in telecommunications requires the use of multichannel time slot interchangers. We propose two multichannel time slot sorters which sort N² time-division multiplexed (TDM) optical inputs, arranged as N frames with N time slots per frame using O(Nlog²N) optical switch elements. The TDM optical inputs are sorted in place without expanding the space-time fabric into a space-division switch. The hardware components used are 2×2 optical switches (LiNbO₃ directional couplers) and optical delay lines connected in a feedforward fashion. Two space-time variants of the spatial odd-even merge algorithm are used to design the sorters. By maintaining the number of shift-exchange operations invariant at each stage, the proposed sorters use fewer switches than previously proposed sorters using switches with feedback line delays. The use of local control at each 2×2 switch makes the proposed sorters more practical for high-speed optical inputs than Benes-based time slot permuters with global control and high latency, which affects interframe distance. Both time slot sorters support pipelining of input frames and sorted outputs are available at each time slot after an initial frame delay. The proposed sorters find practical application in the time-domain equivalents of space-division, nonblocking, self-routing packet switches using the sort-banyan architecture, such as the Starlite switch, Sunshine switch, etc     

Design and implementation of a high-speed matrix multiplier based on word-width decomposition

This paper presents a flexible 2/spl times/2 matrix multiplier architecture. The architecture is based on word-width decomposition for flexible but high-speed operation. The elements in the matrices are successively decomposed so that a set of small multipliers and simple adders are used to generate partial results, which are combined to generate the final results. An energy reduction mechanism is incorporated in the architecture to minimize the power dissipation due to unnecessary switching of logic. Two types of decomposition schemes are discussed, which support 2's complement inputs, and its overall functionality is verified and designed with a field-programmable gate array (FPGA). The architecture can be easily extended to a reconfigurable matrix multiplier. We provide results on performance of the proposed architecture from FPGA post-synthesis results. We summarize design factors influencing the overall execution speed and complexity.     

CMOS high-speed dual-modulus frequency divider for RF frequencysynthesis

The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presented. Compared to other designs fabricated with comparable CMOS technologies, this architecture has a better potential for high-speed operation. The circuit consumes less power than previously reported CMOS circuits, and it approaches the performance previously achieved only by bipolar or GaAs devices. The proposed circuit uses level-triggered differential logic to create an input-frequency-entrained oscillator performing a dual-modulus frequency division. In addition to high-speed and low-power consumption, the divider has a low-input signal level requirement which facilitates its incorporation into RF applications. Fabricated with a 1.2-μm 5-V CMOS technology, the divider operates up to 1.5 GHz, consuming 13.15 mW, and requiring less than 100 mV rms input amplitude     

A reflex optoelectronic switching matrix

A novel method of rapidly composing any required signal delay or combination of delays from a set of precise fixed delay lines is described. Both simple delays and recirculating delay loops can be obtained. The construction of programmable ring resonators with both optical and electrical delay lines is demonstrated. Tunable comb filters with bandwidths up to 1 GHz were obtained. Since delays can be altered within nanoseconds, many applications in digital and analog signal processing can be realized.     

Photo-injection p-i-n diode switch for high-power RF switching

The high RF power-switching properties of the photo-injection p-i-n switch (PIPINS), an optically controlled RF switch, are investigated. Proper functioning of a PIPINS as a low insertion-loss RF switch requires that it operates as a photoconductor, where the photo-injected charge is much greater than the RF sweep out charge. Insertion loss using 650-mW optical power was <0.4 dB at RF (VHF-UHF) power in excess of 200 W, and devices successfully standoff 200-W incident RF power with the series isolation being determined by the device capacitance (e.g., 225 fF). PIPINS hot-switching measurements are reported for the first time, with output RF power up to 180 W at low duty cycle, rise times of 1 ps, and fall times for a series shunt switch of ≈2.5 μs. The RF power for hot switching a PIPINS is limited by a latch-on effect, which is dependent on a variety of parameters, including duty cycle and repetition period, consistent with thermally generated carriers contributing to the latch-on effect. The switching properties of PIPINS make them a candidate for high RF power applications such as reconfigurable antennas, where electromagnetic isolation of the switch and control lines are critical     

High-power RF switching using III-nitride metal-oxide-semiconductor heterojunction capacitors

We propose and demonstrate a novel III-Nitride high-power robust RF switch using SiO/sub 2/-AlGaN-GaN metal-oxide-semiconductor heterojunction (MOSH) capacitors. A metal electrode deposited on the top of the SiO/sub 2/ layer and the low-resistivity two-dimensional electron gas (2DEG) channel at the AlGaN-GaN interface serve as the MOSH capacitor plates. Two "back-to-back" connected MOSH capacitors form a double MOSH (D-MOSH) RF switch thereby eliminating the need for ohmic contacts and also allowing fully self-aligned fabrication. The D-MOSH switch has a symmetrical /spl pi/-type capacitance-voltage characteristic with a static ON-OFF capacitance ratio greater than 20:1. The RF switch exhibits similar polarity independent sharp /spl pi/-type transmission bias curve. At 2GHz, a single-element multifinger D-MOSH switch shows isolation greater than 25 dB and insertion loss of 0.7 dB. The switching power exceeds 60 W/mm making the novel D-MOSH switch robust device for high-power high-temperature integrated electronics.     

Reliability assessment of a plastic encapsulated RF switching device

In this study the degradation and reliability of a plastic encapsulated RF switching device were assessed by comparing several lots of a device that came directly off the assembly line to several other lots which had been subjected to accelerated stress testing. Comparisons of the structure, die and wirebonds were based on the results of examinations using optical microscopy, X-ray analysis, scanning acoustic microscopy, environmental scanning electron microscopy and wire bond pull tests.