Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations

A method is proposed to compensate for local delay variations by adjusting the supply voltage of individual circuit blocks. In-situ characterization of sub-blocks allows for voltage adjustment with minimum safety margin. Different strategies and circuit techniques for in-situ delay characterization of sub-blocks are described and compared. A dual V_DD/power switch scheme is proposed for discrete voltage assignment to individual sub-blocks. Experimental results are presented for a test module based on an ARM9 core, fabricated in 130-nm CMOS. Yield improvement and power reduction capabilities are demonstrated by Monte Carlo simulations. For a typical setting, a reduction of 10% in power can be achieved with the proposed dual V_DD/power switch concept. Using more than two supply voltages is shown to produce only small additional power savings at the price of high area overhead. The effect of the proposed scheme increases with increasing intra-die variability, which makes it suitable especially for future technologies.     

CMOS buffer using complementary pair of bulk-driven super source followers

A power-efficient rail-to-rail CMOS analogue voltage buffer is presented. It consists of a complementary pair of super source followers, but a bulk-driven input device with the replica-biased scheme is utilised to eliminate the DC level shift, quasi-floating gate transistors to achieve class-AB performance, and a current switch which shifts between the complementary pair to allow rail-to-rail operation. The proposed buffer has been designed for a 0.35 mum CMOS technology to operate at a 1.8 V supply voltage. Simulated results are provided to demonstrate the total harmonic distortion for a 1.6 Vpp 100 kHz sine wave with a 68 pF load is as low as -46 dB, while the static current consumption remains under 8 muA.     

A High-Power CMOS Switch Using A Novel Adaptive Voltage Swing Distribution Method in Multistack FETs

A high-power CMOS switch using a novel adaptive voltage swing distribution method in a multistack field-effect transistor (FET) scheme is proposed. The proposed adaptive voltage swing distribution method in multistack FETs is very effective in preventing unwanted channel formation with low control voltage supply in OFF-state FETs. This, in turn, increases power-handling capability when a large-signal voltage swing is applied. In the proposed CMOS switch, the behavior of the voltage swing in OFF-state multistack FETs shows a difference with respect to the level of input voltage swing. The characteristics of voltage swing distribution and leakage channel formation in the CMOS switch is fully analyzed with incorporation of the novel adaptive voltage swing distribution method into a three-stacked nMOS Rx switch in a standard 0.18-mum triple-well CMOS process. In addition, linearity of the proposed technique is verified through the measurement data of the single-pole double-throw switches that employ the proposed technique in the Rx switch. Two different types of configurations are implemented and characterized at the Rx switches, which consist of four-stacked nMOS devices, to demonstrate the method of minimizing voltage stress issues on one of the multistacked FETs. Layout consideration was also taken to prevent interference between leakage signals at the substrate. The measured performance of the proposed design shows an input 0.3-dB compression point of 33.5 dBm at 1.9 GHz. To the best of our knowledge, this is the highest power-handling capability of a CMOS switch in a standard CMOS process ever reported. The insertion losses of the Tx and Rx switches are 1.6 and 1.9 dB, respectively, at 1.9 GHz. The isolation of the Tx and Rx switches is around 20 and 30 dB, respectively, at 1.9 GHz.     

Active series switch for switched-opamp circuits

A series switch to be used in switched-opamp circuits is proposed. The circuit can be implemented in standard CMOS technology and allows rail-to-rail input and output signals to be processed without a voltage multiplier. Using a 0.5 μm CMOS technology, with a 1 V supply, the circuit exhibits a total harmonic distortion better than -60 dB for a differential signal amplitude up to 1.8 Vpp     

低压工作的高速10bit Pipelined ADC

本文提出了一种低压工作的高速1Obit Pipelined ADC。采用自举时钟采样和Cascode频率补偿等方法,该ADC可以在低电压下工作,并达到较高的带宽。该ADC在HJTC 0.18-μm CMOS数模混合工艺下进行了设计仿真和流片测试,结果表明：当供电电压为1．8V,采样频率为62．5MSample／s时,所设计的ADC对于1MHz的输入信号转换有效位数可以达到52．2dB SFDR、44．8dB SNR和44．3dB SNDR。     

Merged CMOS/bipolar current switch logic (MCSL)

A merged CMOS/bipolar current switch logic (MCSL) is presented. CMOS/ECL level conversion and logical operation are realized simultaneously. This circuit technique allows a supply voltage reduction to 3.3 V. A carry delay time of 150 ps/bit for a 4-bit BiCMOS full adder was measured. This is about five times faster than an optimized CMOS adder.<>     

高电源抑制比的CMOS亚阈值多输出电压基准

基于工作在亚阈值区的MOS器件,运用CMOS电流模基准对CATA和PTAT电流求和的思想．提出一种具有低温漂系数、高电源抑制比（PSRR）的CMOS电压基准源,该电路可同时提供多个输出基准电压,且输出电压可调。该基准源基于CSMC0．5μm标准CMOS工艺,充分利用预调节电路并改进电流模基准核心电路。使整个电路的电源抑制比在低频时达到122dB,温度系数（TC）在0-100℃的温度范围内约7ppm／℃。     

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed.In the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the differential comparator,which allows the differential input transistors still to operate in the saturation region at the comparing time.This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage.Additionally,it also features a larger input swing,less sensitivity to common mode voltage,and a simple relationship between the input and reference voltage.This proposed comparator with two traditional comparators has been realized by SMIC 0.13μm CMOS technology.The contrast experimental results verify these advantages over conventional comparators.It has been used in a 12-bit 100-MS/s pipeline ADC.     

A 5.2-GHz CMOS T/R Switch for Ultra-Low-Voltage Operations

A novel CMOS transmit/receive (T/R) switch suitable for ultra-low-voltage operations is presented in this paper. Due to the use of $LC$ resonators in the receiving and transmitting paths, enhanced performance in terms of insertion losses and isolation can be achieved. In addition, the forward-body-bias and body-floating techniques are also introduced to minimize the on-resistance of the MOSFETs at a reduced bias voltage. Using a standard 0.18-$mu{hbox {m}}$ CMOS process, a 5.2-GHz asymmetric T/R switch based on the proposed architecture is implemented. With a supply voltage of 0.6 V, the fabricated circuit exhibits 1.56-dB insertion loss, 17-dB isolation, and 11.2-dBm $P_{{rm in}-1 {rm{dB}}}$ in the receiving mode while the measured results in the transmitting mode are 2.02 dB, 31 dB, and 29.6 dBm, respectively.      

Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies

Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4- V_PP differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and -56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches.     

A low power CMOS voltage reference generator with temperature and process compensation

A low power CMOS voltage reference with process compensation is presented in TSMC 0.18-μm standard CMOS technology. Detailed analysis of the process compensation technique is discussed. The circuit is simulated with Spectre. Simulation results show that, without any trimming procedure, the output voltage achieves a maximum deviation of 0.35 % across different process corners. The temperature coefficient of the proposed circuit is 12.7 ppm/°C in a temperature range from ?40 to 85 °C and the line sensitivity is 0.036 mV/V with a supply voltage range from 1.2 to 2.5 V under typical condition. The maximum supply current is 390.4 nA at maximum supply voltage and ?40 °C. The power supply rejection ratio is ?68.3 dB at 100 Hz and 2.5 V without any filtering capacitor.     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

Optimised analytic designed 2.5 GHz CMOS VCO

An analytic method for prediction of oscillation amplitude and supply current of differential CMOS oscillators is presented. The validity of this method has been verified by designing an LC CMOS oscillator in a 0.24 /spl mu/m CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.     

A low-voltage, low-power CMOS delay element

A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 μm CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current. The inherent advantage of a CMOS thyristor in low voltage domains enables this delay element to work down to the supply voltage of 1 V while the threshold voltage of the nMOS and pMOS transistors are 840 mV and -770 mV, respectively. The designed delay value is less sensitive to supply voltage and temperature variation than RC-based or CMOS inverter-based delay elements. Temperature compensation and jitter performance in a noisy environment are also discussed     

一种10-ppm/~oC低压CMOS带隙电压基准源设计

在对传统CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈和电阻二次分压技术,提出了一种10-ppm/oC低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路的设计,放大器的输出用于产生自身的电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC 0.35mm CMOS工艺实现,采用Hspice进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

SOI技术的机遇和挑战

本文较为系统地描述了SOI技术的特点,分析了SOI技术中存在的问题和发展的潜力,最后得出了SOI技术将在特征尺寸小于0．1um,电源电压小于1V的新一代集成电路技术中得到了广泛应用。     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

A wide-band T/R switch using enhanced compact Waffle MOSFETs

A wide-band complementary metal oxide semiconductor (CMOS)transmit/receive (T/R) switch using enhanced compact waffle metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The compact waffle layout configuration saves much active area to give a low on-resistance. Furthermore,the low drain-to-substrate capacitance (CDB) in waffle MOSFETs can help reduce high frequency substrate coupling and substrate loss for CMOS radio frequency (RF)/microwave integrated circuits (ICs). A 2-dB higher maximum stable gain/maximum available gain (MSG/MAG)and a 2-GHz higher f/sub max/ are obtained compared with those of conventional multifinger MOSFETs. The CMOST/R switch implemented in a standard 0.35-/spl mu/m CMOS technology gives a low insertion loss of 1.7dB,high isolation of more than 40dB, larger than 15-dB return loss, 7-dBm P/sub 1 dB/ and 13-dBm input IP3 at 900MHz with a 3-V supply voltage. The switch maintains a wide-band performance up to 2.4GHz with only a slight deterioration.