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主要介绍了三种可测性设计(DFT)技术,分别是:扫描设计(Scan Design)、边界扫描设计(Boundary Scan Design)和内建自测试设计(BIST)。对于这三种设计技术,分别介绍了其原理和设计过程。 相似文献
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随着集成电路的规模不断增大,集成电路的可测性设计正变得越来越重要.综述了可测性设计方案扫描通路法、内建自测试法和边界扫描法,并分析比较了这几种设计方案各自的特点及应用策略. 相似文献
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本文介绍了一款异构多核DSP芯片的可测性设计实现,包含存储器内建自测试、存储器修复、扫描链设计、测试压缩和全速扫描测试。文章首先对芯片架构和可测性设计难点进行了介绍,并制定了全芯片可测性设计的策略,随后介绍了具体的实现,最后给出了覆盖率结果。实验结果表明该设计的测试覆盖率符合工程应用要求。 相似文献
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介绍了集成电路可测性设计的概念和分类方法,然后以数字调谐系统芯片DTS0614为例,具体介绍了其中的一种即针对性可测性设计方法,包括模块划分、增加控制线和观察点.最后给出了提高电路可测性的另一种方法--内建自测试方法. 相似文献
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从可测性设计与VLSI测试、VLSI设计之间的关系出发,将与可测性设计相关的VLSI测试方法学、设计方法学的内容有机地融合在一起。文中简要地介绍了VLSI可测性设计的理论基础和技术种类,简明地评述了可测性设计的现状和发展趋势,并且探讨了可测性设计的实现方法。 相似文献
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Integration of partial scan and built-in self-test 总被引:2,自引:0,他引:2
Partial-Scan based Built-In Self-Test (PSBIST) is a versatile Design for Testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. PSBIST builds its BIST capability on top a partial scan structure by adding a test pattern generator, an output data compactor, and a PSBIST controller in a way similar to that of deriving a full scan BIST from a full scan structure. However, to make the scheme effective, there is a minimum requirement regarding which flip-flops in the circuit should be replaced by scan flip-flops and/or initialization flip-flops. In addition, test arents are usually added to boost the fault coverage to the range of 95 to 100 percent. These test points are selected based on a novel probabilistic testability measure, which can be computed extremely fast for a special class of circuits. This ciass of circuits is precisely the type of circuits that we obtain after replacing some of the flip-flops.withscan and/or initilization flip-flops. The testability measure is also used for a very useful quick estimation of the fault coverage right after the selection of sean flip-flops, even before the circuit is modified to incorporate PSBIST capability. While PSBIST provides all the benefits of BIST, it incurs lower area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage. 相似文献
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There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.This work was supported by the Defense Advanced Research Projects Agency and monitored by the Federal Bureau of Investigation under Contract No. JFBI90092. The views and conclusions considered in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government. 相似文献
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数字集成电路故障测试策略和技术的研究进展 总被引:9,自引:0,他引:9
IC制造工艺的发展,持续增加着VLSI电路的集成密度,亦日益加大了电路故障测试的复杂性和困难度。作者在承担相应研究课题的基础上,综述了常规通用测试方法和技术,并分析了其局限性。详细叙述了边界扫描测试(BST)标准、可测性设计(DFT)思想和内建自测试(BIST)策略。针对片上系统(SoC)和深亚微米(VDSM)技术给故障测试带来的新挑战,本文进行了初步的论述和探讨。 相似文献
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I. P. Litikov 《Journal of Electronic Testing》1991,1(4):301-304
Here we propose a new approach to the testing of digital devices, which can potentially save diagnostic hardware. An example is given for testing combinational devices. Estimates are given for reliability and hardware complexity, and an algorithm for designing operability tests is described. 相似文献
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This paper introduce a new design for testability methodology for sequential circuits based on input/output pin utilization which exploits the possibility of applying test patterns in parallel. The goal is to reduce the test application time maintaining the same fault coverage as the one obtained using full scan. The proposed procedure includes necessary and sufficient conditions which are easily incorporated in a design system and produce the required implementation. Successful experimental results are presented on benchmark circuits:IC test length is reduced on an average by 44% of full scan.This work is partly supported by research grants from the Natural Sciences and Engineering Research Council of Canada and equipment grants from the Canadian Microelectronics Corporation. 相似文献
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针对高复杂度芯片的生产制造缺陷难以进行充分测试的难题,文中将Mentor公司的4款可测性设计软件集成到芯片前端设计开发流程中,构建相应的设计开发环境。基于此开发环境设计AES算法硬件单元的过程表明,可测试性设计工具能相互配合,很好地支持复杂电路,辅助设计人员正确生成存储器内建自测试电路、边界扫描电路、内部扫描链等多种测试电路,提高了电路的可测试性。 相似文献
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基于部分扫描的低功耗内建自测试 总被引:1,自引:0,他引:1
在分析全扫描内建自测试 (BIST)过高测试功耗原因的基础上 ,提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗 BIST。实验表明 ,提出的方法在保证测试覆盖率的条件下能同时降低 BIST的峰值功耗和平均功耗 ,降幅分别高达 46%和 69%。 相似文献
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