Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization

A study is made of noise in p- and n-channel transistors incorporating SiGe surface and buried channels, over the frequency range f=1 Hz–100 kHz. The gate oxide is grown by low temperature plasma oxidation. Surface n-channel devices are found to exhibit two noise components namely 1/f and generation–recombination (GR) noise. It is shown that the 1/f noise component is due to fluctuations of charge in slow oxide traps whilst bulk centers located in a thin layer of the semiconductor close to the channel, give rise to the GR noise component. The analysis of the noise data gives values for the density D_ot of the oxide traps in the SiGe and Si nMOSFETs of the order 1.8×10¹² and 2.5×10¹⁰ cm⁻² (eV)⁻¹, respectively. The density D_GR of the bulk GR centres is equal to 3×10¹⁰ cm⁻² in both the SiGe and Si devices. The electron and hole capture cross-sections for these centres as well as their energy level and their depth below the oxide/semiconductor interface are also the same in the devices of both types. This suggests that those GR centers are of the same nature in all devices studied. p-Channel devices show different behaviour with only a 1/f noise component apparent in the data over the same frequency range. Buried SiGe channel and Si control devices exhibit quite low and similar slow state densities of the order low to mid 10¹⁰ cm⁻² (eV)⁻¹ whereas surface p-channel devices show even higher slow state densities than n-channel counterparts. The Hooge noise characterized by the Hooge coefficient _H=2×10⁻⁵ is also detected in some buried p-channel SiGe devices.     

Impact of Gate Electrodes on $hbox{1}/f$ Noise of Gate-All-Around Silicon Nanowire Transistors

The low-frequency (1/f) noise of gate-all-around silicon nanowire transistors (SNWTs) with different gate electrodes (poly-Si gate, doped fully silicided (FUSI) gate, and undoped FUSI gate) is studied in the strong-inversion linear region. It shows that the gate electrodes have a strong impact on the 1/f noise of the SNWTs. The highest noise is observed in the SNWTs with a poly-Si gate, compared to their FUSI-gate counterparts. The observations are explained according to the number fluctuation with correlated mobility fluctuation theory by assuming that the correlated mobility scattering is better screened in the case of an undoped FUSI gate. However, the doped FUSI gate with silicidation-induced impurity segregation at the gate/SiO₂ interface gives rise to extra mobility scattering.     

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

We report the first demonstration of a novel germanium-enrichment process for forming a silicon-germanium (SiGe) source/drain (S/D) stressor with a high Ge content. The process involves laser-induced local melting and intermixing of a Ge layer with an underlying Si_0.8Ge_0.2 S/D region, leading to a graded SiGe S/D stressor with a significant increase in the peak Ge content. Various laser fluences were investigated for the laser annealing process. The process is then successfully integrated in a device fabrication flow, forming strained silicon-on-insulator p-channel field-effect transistors (p-FETs) with a high Ge content in SiGe S/D. A drive current enhancement of ~ 12% was achieved with this process, as compared to a strained p-FET with Si_0.8Ge_0.2 S/D p-FETs. The I _Dsat enhancement, primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate lengths.     

Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance

Strained p-MOSFETs with silicon-germanium (SiGe) source and drain (S/D) stressors were fabricated on thin-body silicon-on-insulator (SOI) substrate using a novel local oxidation or Ge condensation technique. By directly growing SiGe on the S/D regions and followed by a local Ge condensation process, the challenges imposed on Si recess etch on thin-body SOI substrates can be alleviated. In the Ge condensation step, the Ge content in the S/D regions may also be increased. At a gate overdrive of -1 V, strained p-MOSFETs show an enhancement in the saturation drive current I_on of up to 38% over the control p-MOSFETs. This significant I_on enhancement is attributed to strain-induced band structure modification, which reduces the hole effective mass along the transport direction. The improved series resistance of the strained devices with SiGe S/D accounted for approximately one-third of the I_on enhancement.     

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

It has been known that using selective epitaxial growth (SEG) of silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f/sub max/) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on DC and RF performance of NMOS transistors. Up to a 28%-45% improvement in f/sub max/ is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain (/sup E/S/D) architecture. The maximum transconductance (g/sub m/) of the /sup E/S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f/sub T/ of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.     

纳米级应变硅MOSFET的有限元与TCAD模拟研究

基于有限元方法对一款具有SiGe源/漏结构的纳米PMOSEFT进行了建模与分析,沟道应变的计算结果与CBED实验测量值呈现良好的一致性,最小误差仅为1.02×10-4.对新型的SiC源/漏结构的纳米NMOSFET的类似研究表明,栅长越短,应变对沟道的影响越显著.另一方面,采用TCAD工具Sentaurus通过工艺级仿真...     

New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.      

W-band double-balanced down-conversion mixer with marchand baluns in silicon-germanium technology

Presented is a monolithic W-band (75-110 GHz) down-conversion mixer consisting of a double-balanced core, Marchand-type on-chip baluns at inputs, and a two-stage output buffer, fabricated in a 200 GHz f _T SiGe technology. Including the loss for input baluns, this mixer exhibits conversion gains of 14.4 plusmn 2.8 dB and single sideband (SSB) noise figures of less than 19.5 dB across the entire W-band, drawing 28 mA from a 3.3 V supply.     

AlGaN/GaN HEMT With a Transparent Gate Electrode

AlGaN/GaN high-electron-mobility transistors (HEMTs) with indium tin oxide (ITO) transparent gate electrodes have been fabricated. The transparent gate electrodes enable the investigation of photon, electron, and phonon behaviors in active regions in HEMTs using optical characterizations such as electroluminescence, photoluminescence, and Raman spectroscopy technologies. Leakage current, on/off ratio, and transparency have been compared for transistors using Ni/Au/Ni, ITO, and Ni/ITO stacks as gate electrodes. Compared to the Ni/Au/Ni gate transistor, the ITO gate device shows a comparable current gain cutoff frequency (f _T) but a much lower power gain cutoff frequency (f _max) due to the low conductivity of ITO.     

Strained ${rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance

A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I_DSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.     

CMOS on dual SOI thickness for optimal performance

A novel strained SOI process with dual SOI thickness has been demonstrated for the first time. Two different SOI thicknesses (Tsi) are obtained on the same wafer for n- and p-channel devices using one additional photo masking step. Device data shows the S/D junction capacitance is reduced by 12% without any degradation in the driving current. A thicker SOI is used for p-channel devices to increase the SiGe recess depth and volume for the embedded S/D SiGe. The driving current is improved by 15% as a result of the larger compressive stress compared to a smaller SOI thickness. Dual SOI thickness is proved to be a viable strategy for independently optimizing n- and p-channel devices.     

1/f noise in amorphous silicon and hydrogenated amorphous silicon thin films

Excess noise measurements have been carried out on either sputtered a-Si or sputtered a-Si:H thin films, at 300 K and in the absence of light. The dependence of excess noise amplitude on hydrogen partial pressure in the sputtering chamber during the film growth has been studied. Investigations of 1/f noise in B-doped a-Si:H thin films have also been carried out. The results of this study show that1/f noise can be correlated to both the hydrogen content in a-Si:H films and to the doping of the films. The noise is explained in terms of fluctuations in the number of gap states due to thermally activated configurational changes involving hydrogenated bonds and dangling bonds.     

30-nm InAs Pseudomorphic HEMTs on an InP Substrate With a Current-Gain Cutoff Frequency of 628 GHz

We report on InAs pseudomorphic high-electron mobility transistors (PHEMTs) on an InP substrate with record cutoff frequency characteristics. This result was achieved by paying attention to minimizing resistive and capacitive parasitics and improving short-channel effects, which play a key role in high-frequency response. Toward this, the device design features a very thin channel and is fabricated through a three-step recess process that yields a scaled-down barrier thickness. A 30-nm InAs PHEMT with t _ins = 4 nm and t _ch = 10 nm exhibits excellent g _m, _max of 1.62 S/mm, f _T of 628 GHz, and f _max of 331 GHz at V _DS = 0.6 V . To the knowledge of the authors, the obtained f _T is the highest ever reported in any FET on any material system. In addition, a 50-nm device shows the best combination of f _T= 557 GHz and f _max = 718 GHz of any transistor technology.     

Spacer-First Damascene-Gate FinFET Architecture Featuring Stringer-Free Integration

This letter presents a new Damascene-gate FinFET process that inherently suppresses stringers, resulting from gate and spacers patterning. The so-called spacer-first integration scheme relies on the engineering of a hydrogen silsesquioxane layer by electron beam lithography followed by two selective compartmentalized development steps to successively release the Damascene-gate cavity and the source/drain (S/D) contact regions. In contrast to the existing gate-first and gate-last integration approaches, the resulting FinFET process does not impose any restriction or interdependency on the sizing of the fins, gate, spacers, and S/D regions. A complete morphological and electrical validation is proposed in the particular case of wrap-around self-aligned metallic Schottky S/D contacts.     

Introduction of local tensile strain on Ge substrates by SiGe stressors selectively grown on wet chemically recessed regions for strained Ge-nMOSFETs

Introduction of tensile strain into Ge substrates was demonstrated by forming embedded SiGe stressors on the recessed regions formed by an anisotropic wet chemical etching process for strained Ge-nMOSFETs having high electron mobility. A damage-free and well controlled anisotropic wet chemical etching process is developed in order to avoid plasma-induced damages in a conventional RIE process. The uni-axial tensile strain over 1% near the Ge recess-edge regions, which is induced by the embedded SiGe stressors, is also demonstrated for the first time. These results suggest that higher electron mobility than the upper-limit for a Si-MOSFET is obtainable in short channel strained Ge-nMOSFETs with the embedded SiGe stressors.     

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si_0.77Ge_0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm^-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.     

Characterization and profile optimization of SiGe pFETs onsilicon-on-sapphire

We present the details of the fabrication, electrical characterization, and profile optimization of a SiGe pFET on silicon-on-sapphire (SOS) technology. The results show that the SiGe pFETs have higher low-field mobility (μ_eff), transconductance (g_m), and cutoff frequency (f_T) than a comparable Si pFET. At low temperature (85 K), a secondary peak is observed in the linear g_m of the SiGe pFETs and is attributed to hole confinement in the SiGe channel. The effect of reducing the SOS film thickness on the mobility and short-channel performance is studied. A low-frequency noise study shows significant improvement in the SiGe pPETs over comparable Si pFETs, and is attributed to a lower sampling of interface trap density caused by the band offset at the oxide interface due to SiGe. Drain Induced Back Channel Inversion (DIBCI) is shown to occur in short gate length devices, resulting in high off-state leakage current through conduction at the back silicon-sapphire interface. The paper also discusses important optimization issues in the design of 0.25-μm gate length SiGe pFETs. A novel structure is proposed which optimizes the threshold voltage, maximizes hole confinement gate voltage range and cutoff frequency, while at the same time minimizing DIBCI to make the design usable to gate lengths as short as 0.25 μm     

Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior

In this letter, we investigate the effects of process-induced strain on negative bias temperature instability (NBTI) by performing a comparative study of devices with and without process-induced strain for poly-Si/SiON gate stacks. Devices with SiGe source/drain with different processing sequences and devices with a combination of SiGe S/D and compressive contact etch stop layer (CESL) were studied and compared to reference devices. We decouple the effect of processing conditions in order to ensure a correct interpretation of the results. In contrast with the previous reports, which did not consider the impact of processing conditions, this letter demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with a process-induced strain. In addition, we performed an Arrhenius study showing similar activation energies for devices with and without process-induced strain, suggesting similar degradation mechanism. The results indicate that process-induced strain does not create favorable conditions for additional interface state creation