具有低功耗和高性能的可配置处理器内核

可配置处理器内核第七代产品Xtensa LX2和Xtensa 7具有低功耗和高性能的特点，内建高速纠错EC功能，使IC设计师可采用自动处理器生成器向基本处理器添加专用指令。Xtensa 7和Xtensa LX2处理器内核降低了近30％功耗（内核加上存储器），主要技术包括：可分别配置主系统存储器接口、本地数据存储器接口和指令存储器接口等诸项接口的宽度；     

嵌入式系统的低功耗设计

本质上,低功耗设计并不需要魔法,但的确需要极大的努力关注和处理各种细节。     

一种低功耗Cache设计技术的研究

低功耗、高性能的cache系统设计是嵌入式DSP芯片设计的关键。本文在多媒体处理DSP芯片MD32的设计实践中，提出一种利用读／写缓冲器作为零级cache，减少对数据、指令cache的读／写次数，由于缓冲器读取功耗远远小于片上cache，从而减小cache相关功耗的方法。通过多种多媒体处理测试程序的验证，该技术可减少对指令cache或者数据cache20％～40％的读取次数，以较小芯片面积的增加换取了较大的功耗降低。     

用Xtensa可配置处理器实现高性能低功耗系统

可配置处理器允许嵌入式开发人员来定制适合目标算法的处理器,使得处理器和算法能够更好地匹配。设计人员可以增加专用的、可变宽度的寄存器,专用的执行部件和更宽的数据总线以达到专用算法的最优处理器配置。加速FFT运算按频率抽取快速傅立叶变换FFT算法的核心是一种称为“蝶形”的运算。蝶形操作是FFT算法的最里层循环的运算。每个蝶形运算需要六次加法和四次乘法来计算基2蝶形结果的实部和虚部。采用TI(ETensilicaIn-structionExtention)语言,设计团队可以用四个加法器和两个乘法器来扩展整个Xtensa处理器的流水线,以便使得一半F…     

基于Load重用的低功耗数据Cache设计

针对嵌入式处理器中数据Cache功耗显著的特点,提出了一种基于Load重用的低功耗数据Cache设计方法.通过保存Load指令从数据Cache中取回的数据,实现了随后Load指令对该数据的重新使用,从而减少了数据Cache的访问次数,有效降低了数据Cache的功耗.在SuperV_EF01DSP上的实验结果显示,采用该方法后,在处理器性能没有损失的情况下,数据Cache功耗平均降低29.48%,面积仅增加0.64%.     

嵌入式Linux-简化基于可配置处理器的Linux研发

Tensilica和Timesys宣布针对Tensilica钻石标准232L,处理器提供LinuxLink订阅服务。LinuxLink订阅服务为开发者提供专为Tensilica232L钻石标准处理器测试和集成的全套嵌入式Linux平台,包括Linux2．625Kernel、232L专用设备驱动、基于GNU μClibc的工具链及数百个预先汇编的软件包。     

一种gshare分支预测器的低功耗设计方法

功耗与性能在高端嵌入武计算系统中都是非常重要的设计指标。基于深度流水处理器中所使用的动态分支预测器的微结构特点，提出了一种利用分页技术来有效的降低gshare分支预测器的功耗的设计方法，详细分析了分支预测器的大小、分页数以及功耗、面积之间的内在关系。     

台湾地区IC设计公司引入Tensilica可配置处理器

Tensilica公司日前宣布，位于台北的Afa Technlolgies，Inc．（简称Afa）选择xtensa可配置处理器内核用于最新一个支持多标准的手机数字电视接收SoC设计项目。Afa是一家无工厂IC设计服务公司，专精于DTV（数字电视）、手机和数字家庭LAN（局域网）芯片设计。     

低功耗嵌入式实现的方方面面

在嵌入式应用中,影响功耗指标的因素很多.在进行具体设计预算时,了解这些因素将有助于设计出理想的低功耗系统.本文将考虑影响功耗的不同方面,同时,这些知识对于某个特定项目的处理器选择也有帮助.     

嵌入式行业盛行低功耗和可配置

提出了嵌入式领域出现了低功耗和可配置潮流。微控制器领域的低功耗产品介绍了Microchip休眠电流低至20nA的nano Watt XLP产品,以及NXP的基于Cortex-M0的LPCI1004低功耗芯片。FPGA厂商Xilinx推出了“目标设计平台”领域的专用设计方法——ISE设计套件11．1解决方案,为FPGA应用推波助澜。     

Multi-bit upset aware hybrid error-correction for cache in embedded processors

For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multi-bit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.     

一种新的基于可配置处理器的异构多核线程级动态调度模型

本文针对基于可配置处理器的异构多核结构,提出一种新的线程级动态调度模型。此类异构多核系统中每个核分别针对某一应用做指令集扩展,调度器通过线程、处理器核以及指令集间的映射关系,动态调度线程至适合的处理器核,从而在没有大幅增加芯片面积的前提下,达到与每个核都具有全扩展指令集相近似的加速比,此外该模型还可以有效减少编程模型的复杂度。     

PEM:a lightweight program memory encryption mechanism for embedded processor

Application of embedded systems is faced with multiple threats against security.To solve this problem,this article proposes a new program memory encryption mechanism(PEM) to enhance the security of embedded processor.The new mechanism encrypts all the programs via a secure cache structure.It not only caches the instructions read from the off-chip memory,but also stores the pad values used to encrypt the plaintext.It effectively accelerates encryption and reduces the performance overhead.Besides the encrypti...     

嵌入式处理器的定点化运算单元设计

为了满足基于嵌入式处理器的音频解决方案的需要,提出了一种嵌入式处理器中高精度、多功能的定点化运算单元(FPU)。FPU由移位、舍入、饱和3个部分组成。通过对FPU的实现和验证,证明FPU能够显著提高嵌入式处理器定点化操作的速度。     

集成循环代码cache降低微控制器功耗研究

功耗对于面向低成本低功耗应用的微控制器(单片机)十分重要.研究表明,CPU由于取指对程序存储器的访问功耗,构成了微控制器整体功耗的重要组成部分,而微控制器应用程序的大部分执行时间被用于执行固定的循环代码.研究了集成循环代码cache,从中执行循环代码来降低存储器访问功耗的技术.     

A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor

Energy consumption and data stability are vital requirement of cache in embedded processor. SRAM is a natural choice for cache memory owing to their speed and energy efficiency. Noise insertion to the SRAM cell during read is a serious problem which reduces its stability. A read disturbance free differential SRAM cell consisting of seven transistors is proposed here which increases cell stability along with maintaining the most desirable differential read technique for faster read. The read SNM of the proposed cell is 154%, 31% and 58% large than that of the conventional 6T-SRAM cell and 2 other 7T-SRAM cells [5,6] compared here. Various factors such as short circuit current reduction, use of single write access transistor, partial bit line swing etc. reduces the overall energy consumption of the proposed cell by 41% compared to 6T-SRAM cell. The proposed cell is also compared with an eight transistor based read disturbance free SRAM cell. The cell delay of the proposed cell is around 55% lesser than that of the 8T-SRAM cell. Besides CMOS the performance achievement of the proposed 7T-SRAM cell is also validated at miniaturized dimension of 20 nm using FinFET based predictive technology model library.     

RDMM: Runtime dynamic migration mechanism of distributed cache for reconfigurable array processor

Reconfigurable array processors have emerged as powerful solution to speed up computationally intensive applications. However, they may suffer from a data access bottleneck as the frequency of memory access rises. At present, the distributed cache design in the reconfigurable array processor has a large cache failure rate, and the frequent access to external memory leads to a long delay in memory access. To mitigate this problem, we present a Runtime Dynamically Migration Mechanism (RDMM) of distributed cache for reconfigurable array processor based on the feature of obvious locality and high parallelism in accessing data. This mechanism allows temporary, static data to be dynamically scheduled to migrate data with a high access frequency from the remote cache to the processor's local migration storage table based on how often the reconfigurable array processors access the remote cache. We can accurately get the data on the shortest path by way of data search strategy based on migration storage tables, thereby effectively reducing the access delay of the entire system, increasing the memory bandwidth of the reconfigurable array processor. We leverage the hardware platform of reconfigurable array processor to test the proposed mechanism. The experimental results show that RDMM reduces access delay by up to 35.24% compared with the tradition distributed cache at the highest conflict rate. And compared with the Ref.[19], Ref.[20], Ref.[21] and Ref.[23], the working frequency can be increased by 15%, the hit rate can be increased by 6.1%, and the peak bandwidth can be increased by about 3×.     

嵌入式DSP访问片外SDRAM的低功耗设计研究

为了降低DSP外部SDRAM存储系统的功耗,针对DSP访问片外SDRAM的功耗来源特点,提出了基于总线利用率动态监测的读写归并方案。该方案动态监测外部存储器接口(EMIF)总线的利用率,根据总线利用率的不同选择开放的页策略、封闭的页策略或休眠模式;设计了简化的指令Cache(I-Cache),采用块读的方法取指令;设计了写后数据缓冲区,由EMIF对同一行的读写进行归并。经计算,根据EMIF总线利用率的不同(10%~40%),该方案相比单纯采用开放的页策略,功耗可减少5%~20%左右。     

基于Blackfin处理器的嵌入式数码相框设计

介绍了汇聚式处理器Blackfin的基本功能,给出了以Blackfin为嵌入式系统硬件平台,并采用uClinux操作系统和其中集成的大量硬件驱动程序来设计具有互联网WiFi无线连接、电子邮件发送、RSS新闻阅读、即时照片分享、全触摸操作等功能的嵌入式数码相框的设计方案。     

面向访问需求的数据缓存泄漏功耗管理方法

 本文提出面向访问需求的数据缓存泄漏功耗管理方法,根据访存指令对数据缓存的访问需求控制数据缓存的活动.当流水线中未发现访存指令时,将整个数据缓存保持在非活跃状态;而当发现访存指令进入流水线时,采用两种数据缓存访问控制策略以及对这两种策略的动态选择机制,在流水线早期捕获访存地址的访问需求,对数据缓存的活动作出精细控制.实验结果表明,在平均情况下,本文方法将数据缓存的泄漏功耗降低85.4%,而处理器性能提升4.41%,比传统方法在功耗与性能方面均达到更优结果.