An Advanced PSA Technology for High-Speed Bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double poly-silicon electrodes, the emitter area is reduced to 1/spl mu/m X 3 /spl mu/m and the base junction is reduced to 0.3 /spl mu/m. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.     

A fine emitter transistor fabricated by electron-beam lithography for high-speed bipolar LSI's

A highly stable, high-performance bipolar transistor with a 1/4-µm emitter is developed. This is accomplished by using advanced electron-beam (EB) lithography and polysilicon reactive ion etching (RIE). Results show that the minimum emitter width is only 0.2 µm and the emitter width accuracy is ±0.06 µm. In addition, the gate delay is reduced from 190 to 100 ps/gate for 25-stage, three-input ECL circuits. The effects of an ultra-narrow emitter on transistor characteristics are also studied.     

A new polysilicon process for a bipolar device—PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSI's. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an emitter-coupled logic (ECL) gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 µm²gate area has been achieved. Futhermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000-µm²gate area has been successfully developed.     

High-speed BiCMOS technology with a buried twin well structure

A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (fT= 4 GHz) and small size (500 µm²) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.     

Annealing of oxide fixed charges in scaled polysilicon gate MOS structures

Annealing of oxide fixed charges (QF) under polysilicon gate in scaled MOS structures was studied. Our results indicate that, even for a gate width as small as 1.25 µm, QFunderneath the polysilicon gate is unaffected by further processing steps, including high-temperature oxidizing ambients. In other words, the QFtriangle reduces to a horizontal line, even for scaled down polysilicon gate MOS devices. This result has important practical implications, because poly-Si gate is the dominating MOS technology today. A two-dimensional oxygen diffusion model is proposed to explain this phenomenon. Numerical solution was carried out based on the finite difference method. It will be shown that the polysilicon gate not only acts as a barrier to oxygen above the gate oxide, it also keeps oxygen away from the SiO_{2}- Si-substrate interface under the gate edges, thus very effectively shielding the gate oxide from the ambient.     

p-Channel MOSFET's in LPCVD PolySilicon

p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-Å n⁺poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as the gate insulator. Then a 1500-Å LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm²/V.s. The drain-to-source breakdown voltage exceeds -20 V.     

A new polysilicon process for a bipolar device-PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSIs. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an ECL gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 /spl mu/m/SUP 2/ gate area has been achieved. Furthermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000 /spl mu/m/SUP 2/ gate area has been successfully developed.     

Technology of a new n-channel one-transistor EAROM cell called SIMOS

The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the floating gate. In the programming mode, electrons are accelerated by the channel drift field to energies high enough to overcome the barrier height of the Si-SiO2interface and so injected into the floating gate. On account of the channel-injection mechanism performed in the programming mode, channel lengths of less than 4 µm are required. A combination of this condition with the stacked-gate concept is achieved by a self-aligned technique which defines both polysilicon gates by a single photolithographic procedure. By means of the self-aligned technique, both the one-transistor EPROM cell and the one-transistor EAROM cell can be realized. Basic structures of the two different type one-transistor memory cells are the SIMOS transistor and the SIMOS tetrode, respectively. The technology of these two different SIMOS devices is described in detail and experimental results concerning charge accumulation, charge removal, and charge retention are reported.     

Submicrometer Silicon MOSFET's fabricated using focused ion-beam lithography

Submicrometer n-channel enhancement-mode silicon MOSFET's with polysilicon gate lengths as small as 0.35 µm were fabricated using focused-ion-beam lithography. The polysilicon gate was patterned by a 80-kV Au-Si ion beam using a negative polystyrene resist. Transconductance values of 140 mS/mm were obtained for devices with gatelengths of 0.4 µm and gate oxide thickness of 10 nm. Short-channel effects were minimal in these devices.     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance     

Small geometry MOS transistor capacitance measurement method using simple on-chip circuits

A method of measuring the gate capacitance of very small geometry devices using simple on-chip circuits is described. Short-channel effects observed in gate capacitance measurements of an MOS transistor with Weff/Leff= 9.2 µm/0.8 µm are presented. Measurement results show that the resolution of the technique is much better than 0.1 fF.     

Gate delays of InGaAs/InP heterojunction integrated injection logic

The delay time of an InGaAs/InP heterojunction bipolar transistor integrated injection logic gate is calculated as a function of the npn transistor upward current gain and for fan-outs of one and four. It is shown that intrinsic gate delays under 300 psec are possible with a fan-out of 4 for a gate designed with 3 µm design rules and having 0.5 µm npn and pnp base widths. Gate delays well under 100 psec are predicted for less conservative designs.     

A vertically isolated self-aligned transistor—VIST

A vertically isolated self-aligned transistor (VIST) has been developed to make possible high-speed low-power dissipation bipolar devices suitable for LSI. This VIST consists of a bird's beak free oxide isolated structure and a high impurity density inactive base self-aligned to the polysilicon emitter. A flat emitter transistor with a self-aligned base is developed by forming an inactive high impurity density base region with an ion-implantation method using a polysilicon emitter as a mask. The transistors exhibit uniform current gain even to current levels as low as 10^-8A. The ftvalue of this transistor is 6 GHz. The ring oscillators and counter are fabricated using the 13 × 6 µm²transistor cell. The power and delay product is 0.12 pJ.     

Titanium nitride local interconnect technology for VLSI

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n⁺and p⁺junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n⁺and p⁺junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils²feasible with 1-µm design rules, is also discussed.     

Composite TiSi2/n + poly-Si low-resistivity gate electrode and interconnect for VLSI device technology

A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi2polycide gate. A coevaporated TiSi2polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi2because of lower oxygen contamination. The coevaporation technique to form TiSi2polycide with a sheet resistivity of 1 Ω/square (bulk resistivity of 21 µΩ.cm) is described. Anisotropic etching of nominally 1-µm lines with a 15:1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi2polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude.     

High-speed, low-power, implanted-buried-oxide CMOS circuits

CMOS ring oscillators with channels less than 1/2 µm long were fabricated in implanted-buried-oxide, silicon-on-insulator films using direct-write electron-beam lithography. Transistors with polysilicon gate lengths as short as 0.4 µm and effective channel lengths as short as 0.21 µm operate satisfactorily. Ring oscillators have delays per gate of 52 and 83 ps and power-delay products of 55 and 5 femtojoules for supply voltages of 5 and 3.3 V, respectively.     

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 μm to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si₃N₄ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6×10⁶ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns     

A 30-ps Si bipolar IC using super self-aligned process technology

A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The fTvalues achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.     

超高速双层多晶硅发射极晶体管及电路

报道了双层多晶硅发射极超高速晶体管及电路的工艺研究．这种结构是在单层多晶硅发射极晶体管工艺基础上进行了多项改进,主要集中在第一层多晶硅的垂直刻蚀和基区、发射区之间的氧化硅、氮化硅复合介质的L型侧墙形成技术方面,它有效地减小了器件的基区面积．测试结果表明,晶体管有良好的交直流特性．在发射区面积为3μm×8μm时,晶体管的截止频率为6.1GHz．19级环振平均门延迟小于40ps,硅微波静态二分频器的工作频率为3.2GHz．