Electrical Measurement of Feature Sizes in MOS Si/sup 2/-Gate VLSI Technology

The reduced device dimensions of VLSI circuits resulting from improved lithographic techniques require very useful control of the feature sizes during the production process. For this purpose, test patterns and measurement techniques for automatic electrical measurements of misalignments and feature sizes have been developed for the control of an MOS Si/sup 2/-gate process. Using these methods, correlations between the electrically relevant device parameters and the feature sizes are obtained. A sensitivity analysis for the threshold voltage has been made. It was found that for the technology under consideration, the variation of the feature sizes predominates over the influences of all other technological parameters at transistor lengths of 1-2 //spl mu/m.     

A new single-chip C/SUP 2/MOS A/D converter for microprocessor systems-Penta-Phase Integrating C/SUP 2/MOS A/D converter

A new unique conversion technique named the `Penta-Phase Integration' method, applied to a single-chip C/SUP 2/MOS 12-bit analog-to-digital converter designed for microprocessor system, is introduced and described. The newly developed device, fabricated with a standard metal gate CMOS process including an 8-channel multiplexer and TTL compatibility, has several features: unipolar- and ratiometric-conversion can be performed; conversion accuracy within /spl plusmn/0.05 percent of full scale over the -35/spl deg/C-+85/spl deg/C temperature range can be obtained; conversion time is 1.1 ms at a 20 MHz clock frequency, and the device can be operated with a single 5 V power supply and 6 mW power consumption at a 4 MHz clock frequency. The new technique essentially incorporated several methods which divide one conversion cycle into five-phases, accomplish minimization of the error caused by comparator response delay, provide several narrow flat phases to eliminate switching errors due to parasitic capacitance, and enable high clock frequency operation in digital circuits by utilizing C/SUP 2/MOS circuit technology and a synchronized configuration for counters.     

Synthesis of single sets of 2/sup n/ mutually orthogonal phase codes

Unique sets of 2/sup n/ phase coded pulses are introduced. Derived from any phase code, using simple transformations, these codes possess the useful property that the sum of all possible cross-correlations added to the sum of all autocorrelations within a set produces a pulse compressed signal. This signal has a peak to sidelobe ratio equal to that for the autocorrelation function of the original untransformed code.<>     

Optimal model matching: H/sup 2/ or H/sup infinity /?

An attempt is made to characterise, qualitatively and quantitatively, the major differences between H/sup infinity / and H/sup 2/-optimal model matching control. Conditions under which the effectiveness of model matching in H/sup infinity /-norm space is superior to that in H/sup 2/-norm space are derived. According to these conditions, designers can easily decide between H/sup infinity / and H/sup 2/ approaches to meet the required performance.<>     

On a Pitch Alteration for Speech Synthesis Systems

Speech synthesis can be classified into waveform coding, source coding, or hybrid coding by the synthesis method. Among these, waveform coding is especially suitable for high-quality speech synthesis. However, synthesis techniques using syllable or phoneme unit is not desirable since it fails to separate the excitation and the formant part to handle speech. Therefore, there is a need for a pitch alteration method to apply in synthesis using waveform coding. This study proposes a pitch alteration method that uses spectrum scaling after flattening the spectra by a sub-band linear approximation to minimize the spectrum distortion. A comparison with LPC (Linear Predictive Coding), Cepstrum and lifter function is presented to show the better performance of the proposed method. Estimation method seeks each of the distributions of the flattened signal and measures the degree of the flattened spectrum Signal, which is normalized, so the highest point amounts to zero, and the distribution of the signal, whose average is zero, is calculated. The results are presented by the spectrum distortion rate to estimate the performance of the proposed method. The average spectrum distortion rate kept below the average 2.12%, showing the proposed method’s superiority in comparison with the other existing approaches.

Addition-based exponentiation modulo 2/sup k/

A novel method for performing exponentiation modulo 2/sup k/ is described. The algorithm has a critical path consisting of k dependent shift-and-add modulo 2/sup k/ operations. Although 3 is the preferred exponent base, the algorithm can be extended easily in order to perform the general binary powering operation.     

A 256-channel C/SUP 2/MOS LSI time-switch using shift-register pipeline multiplexer

SOS technology has been used to retain the pipeline processing speed advantage by controlling the capacitance of on-chip lines that must be long to provide 256-channel operation. Clocked CMOS (C/SUP 2/MOS) circuits have been used to avoid clock-skew problems. A 1.5-/spl mu/m C/SUP 2/MOS/SOS technology has made it possible to integrate 900 transistors into a 4.0/spl times/2.4-mm/SUP 2/ area, and to realize a 256-channel time-switch LSI, with a 15-ns typical output delay time and a 300-mW power dissipation during 25-MHz operation.     

Spectrally efficient full-response Q/sup 2/PSK signals

Based on a novel class of orthogonal pulse pairs, a spectrally efficient full-response quadrature-quadrature phase-shift keying (Q/sup 2/PSK) signal format is proposed. The proposed full-response Q/sup 2/PSK signals can provide higher spectral compactness than conventional full-response Q/sup 2/PSK signal, minimum-shift keying signal and quadrature phase-shift keying signal.     

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

A self-aligned I/sup 2/L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aIigned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-/spl mu/m design roles and fabricated with this technology exhibit gate delays as small as 0.8 ns at lC = 100 -/spl mu/A for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.     

A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio

A 56-mW 23-mm/sup 2/ GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm/sup 2/ radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]/spl deg/C temperature range. The radio draws 17 mA from a 1.6-1.8-V voltage supply, takes 11 pins of a VFQFPN68 package, and needs just a few passives for input match and a crystal for the reference oscillator. Measured radio performances are NF=4.8 dB, Gp=92 dB, image rejection > 30 dB, -112 dBc/Hz phase noise @ 1 MHz offset from carrier. Though GPS radio linearity and ruggedness have been made compatible with the co-existence of a microprocessor, radio silicon area and power consumption is comparable to state-of-the-art stand-alone GPS radio. The one reported here is the first ever single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm/sup 2/ and 56-mW power consumption.     

超大容量语音系统的存贮方法研究

提出了语音合成技术实现时的容量存贮问题,简要介绍了语音参数合成法中较优秀的线性预测编码方法,指出了它在实际应用中存在的困难,介绍了美国TI公司两种改进的预测编码算法MELP和CELP及相应硬件MSP50X3X系列语音合成器的原理,提出了一个应用系统实例,给出了详细的硬件和软件设计。     

2/sup 1///sub 2/ step flash A/D convertor

A simple technique for obtaining an extra bit of resolution from a multistep flash A/D convertor is described. It is shown that when used with a conventional multistep convertor, this technique can give significant savings in chip area and power at the expense of a very small increase in conversion time.<>     

An efficient VLSI design for a residue to binary converter for general balance moduli (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3)

In this paper, we present a new four-moduli set (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3) and an efficient residue to binary (R/B) converter design. The merits of the proposed four-moduli set include 1) larger dynamic range; 2) higher degree of parallelism for conversion; 3) balanced bit-width for internal RNS arithmetic operations; and 4) flexible moduli set selection. According to the relation between the proposed moduli, the divide-and-conquer technique is used to design a two-level converter architecture which has lower hardware cost and shorter critical delay. For the R/B converter designed with 12-b (n=3), our architecture has about 47% saving in hardware cost and 40% saving in critical delay compared to the last work.     

基于分形迭代函数系统的语音合成新算法

本文根据语音信号具有局部自相似性的特点，提出一种基于分形迭代函数系统的语音合成新算法，给出了两种数值解法。与传统的方法相比，本文的方法结构更简单，且合成语音的质量更高。     

100-Gb/s 2/sup 7/-1 and 54-Gb/s 2/sup 11/-1 PRBS generators in SiGe bipolar technology

This paper presents two monolithic pseudorandom bit sequence (PRBS) generators. One circuit uses a seven-stage shift register operating with a half-rate clock and provides output signals up to 100 Gb/s. The second circuit contains an eleven-stage shift register operating with a full-rate clock up to 54 Gb/s. Both PRBS generators provide a wide range of data rates down to below 1 Gb/s simply by changing the frequency of the external clock signal without the need of any further adjustments. The integrated circuits provide a trigger output which can be switched between eye and pattern display. Furthermore, they contain additional circuitry to guarantee automatic start after power-on. The circuits are manufactured in a 200-GHz f/sub T/ SiGe bipolar technology. They each have a chip size of 900/spl times/700 /spl mu/m/sup 2/ and consume 1.5 and 1.9 W, respectively.     

Negacyclic codes of length 2/sup s/ over galois rings

Codes over the ring of integers modulo 4 have been studied by many researchers. Negacyclic codes such that the length n of the code is odd have been characterized over the alphabet Zopf₄, and furthermore, have been generalized to the case of the alphabet being a finite commutative chain ring. In this paper, we investigate negacyclic codes of length 2^s over Galois rings. The structure of negacyclic codes of length 2^s over the Galois rings GR(2^a,m), as well as that of their duals, are completely obtained. The Hamming distances of negacyclic codes over GR(2^a,m) in general, and over Zopf₂ ^a in particular are studied. Among other more general results, the Hamming distances of all negacyclic codes over Zopf₂ ^a of length 4,8, and 16 are given. The weight distributions of such negacyclic codes are also discussed     

Double heterojunction GaAlAs/GaAs I/sup 2/L integrated circuits

The fabrication and DC characterisation of GaAlAs/GaAs double heterojunction bipolar transistors (DHBTs) grown by molecular beam epitaxy are described. This baseline process has been developed for the implementation of heterojunction integrated injection logic (HI/sup 2/L) integrated circuits. Results concerning an I/sup 2/L ring oscillator and a divide-by-two circuit are given.<>     

Additive bit-serial algorithm for discrete logarithm modulo 2/sup k/

A novel algorithm for computing the discrete logarithm modulo 2/sup k/ that is suitable for fast software or hardware implementation is described. The chosen preferred implementation is based on a linear-time multiplier-less method and has a critical path of less than k modulo 2/sup k/ shift-and-add operations.     

Efficient amplification using the /sup 4/F/sub 3/2//spl rarr//sup 4/I/sub 9/2/ transition in Nd-doped silica fiber

Amplification characteristics of the three-level /sup 4/F/sub 3/2//spl rarr//sup 4/I/sub 9/2/ transition in Nd-doped silica glass fiber are investigated under strong signal saturation and high pump power (150 mW). Aluminum codoped Nd-silica fibers exhibit strong superfluorescent behavior in the four-level /sup 4/F/sub 3/2//spl rarr//sup 4/I/sub 11/2/ transition which limits the optical conversion efficiency into the three-level transition. Ge-doped silica fibers do not exhibit this limitation and can efficiently amplify in the three-level transition with current laser-diode pump technology.     

Charge-based chemical sensors: a neuromorphic approach with chemoreceptive neuron MOS (C/spl nu/MOS) transistors

A novel chemoreceptive neuron MOS (C/spl nu/MOS) transistor with an extended floating-gate structure has been designed with several individual features that significantly facilitate system integration of chemical sensing. We have fabricated C/spl nu/MOS transistors with generic molecular receptive areas and have characterized them with various fluids. We use an insulating polymer layer to provide physical and electrical isolation for sample fluid delivery. Experimental results from these devices have demonstrated both high sensitivity via current differentiation and large dynamic range from threshold voltage shifts in sensing both polar and electrolytic liquids. We have established electrochemical models for both steady-state and transient analyses. Our preliminary measurement results have confirmed the basic design and operations of these devices, which show potential for developing silicon olfactory and gustatory units that are fully compatible with current CMOS technology.