An on-chip smart memory for a data-flow CPU

Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional read and write operations. An experimental 1240-b smart memory chip is implemented in a 1.6-μm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34658 transistors, occupies an area of 3.8 mm×5.2 mm, and dissipates 0.51 W     

Why is nonvolatile ferroelectric memory field-effect transistorstill elusive?

In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed     

Anticipatory I/O Management for Clustered Flash Translation Layer in NAND Flash Memory

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two‐level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two‐level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well‐known NAND FTL (NFTL) and adaptive FTL (AFTL).     

A long-refresh dynamic/quasi-nonvolatile memory device with 2-nmtunneling oxide

A memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed. The device achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time. This device has a SRO charge trapping layer on top of a very thin tunneling oxide (<2 nm). Using the traps in the SRO layer for charge storage, a symmetrical write/erase characteristics were achieved. This new SRO cell has an erase time much shorter than values of similar devices reported in the literature     

Strain‐Based Temperature Memory Effect for Nafion and Its Molecular Origins

A shape memory polymer traditionally refers to a polymer that can memorize one temporary shape and recover to its permanent shape upon exposure to an external stimulus. Although this basic concept has been known for at least half a century, recent advances have led to the discoveriy of previously uncovered memory properties that challenge the traditional concept of shape memory polymers. In particular, a temperature memory effect refers to the capability of a polymer to memorize temperatures instead of shapes. Thus far, the reported temperature memory effect has been established under iso‐strain stress recovery conditions, in which the maximum recovery stress appears at a temperature roughly identical to the deformation temperature. This effect can be called recovery stress based temperature memory effect. In this work, experiments were designed in an attempt to establish a temperature memory effect based on the stress free strain recovery behaviors of Nafion. The results show that, under carefully selected conditions, the temperature at which a maximum strain recovery rate is observed can indeed be quantitatively related to the deformation temperature. In addition, indications that the polymer is capable of memorizing more than one deformation temperature (i.e., multi‐temperature memory effect) are shown. The molecular origin of Nafion’s temperature memory effect is elucidated through small angle neutron scattering study.     

Error-Correcting-Code Memory Reliability Calculations

The subject of this paper is the Mean Time to Failure (MTTF) calculation for a computer memory array with error correcting code (ECC) that detects and corrects 1-bit errors in memory words. The MTTF calculation is examined within the framework of the Whole Chip Failure Mode model. This paper has two main contributions: 1) The MTTF equation is derived in a way that is mathematically simpler and easier to understand. 2) An approximation to the exact equation is derived along with bounds on the accuracy of the approximation. This approximation has a simple, intuitive interpretation that relates the ECC case back to the simpler nonECC case. The first result provides insights to readers interested in the theory of memory reliability calculations while the second provides quick estimates to those in need of actual calculations.     

GdO存储层中氧含量及掺氮对MONOS存储器特性的影响

采用反应溅射法制备以GdOx或GdON为存储层的MONOS(Metal-Oxide-Nitride-Oxide-Si)电容存储器,研究了GdOx中氧含量以及掺氮对MONOS存储器存储特性的影响。实验结果表明,含氧气氛中制备的GdO其氧空位(电荷陷阱)较少,且界面处存在较多Gd-Si键,导致界面态密度增加,因而存储特性欠佳;引入氮至GdO中可诱导出大量的深能级电子陷阱,并能提高介电常数、减少界面缺陷,因此GdON样品表现出好的存储特性:较大的存储窗口(±13V/1s的编程/擦除电压下,存储窗口4.1V)、高的工作速度、好的保持特性以及优良的疲劳特性(105循环编程/擦除后,存储窗口几乎不变)。     

Memory sub-banking scheme for high throughput MAP-based SISO decoders

The sliding window (SW) approach has been proposed as an effective means of reducing the memory requirements as well as the decoding latency of the maximum a posteriori (MAP) based soft-input soft-output (SISO) decoder in a Turbo decoder. In this paper, we present sub-banked memory implementations (both single port and dual port) of the SW SISO decoder that achieves high throughput, low decoding latency, and reduced memory energy consumption. Our contributions include derivation of the optimal memory sub-banked structure for different SW configurations, study of the relationship between memory size and energy consumption for different SW configurations and study of the effect of number of sub-banks on the throughput/decoding latency for a given SW configuration.     

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

Error correction codes (ECCs) are commonly used to deal with soft errors in memory applications. Typically, Single Error Correction-Double Error Detection (SEC-DED) codes are widely used due to their simplicity. However, the phenomenon of more than one error in the memory cells has become more serious in advanced technologies. Single Error Correction-Double Adjacent Error Correction (SEC-DAEC) codes are a good choice to protect memories against double adjacent errors that are a major multiple error pattern. An important consideration is that the ECC encoder and decoder circuits can also be affected by soft errors, which will corrupt the memory data. In this paper, a method to design fault tolerant encoders for SEC-DAEC codes is proposed. It is based on the fact that soft errors in the encoder have a similar effect to soft errors in a memory word and achieved by using logic sharing blocks for every two adjacent parity bits. In the proposed scheme, one soft error in the encoder can cause at most two errors on adjacent parity bits, thus the correctness of memory data can be ensured because those errors are correctable by the SEC-DAEC code. The proposed scheme has been implemented and the results show that it requires less circuit area and power than the encoders protected by the existing methods.     

PERFORMANCE COMPARISON OF CELL－BASED AND PACKET－BASED SWITCHING SCHEMES FOR SHARED MEMORY SWITCHES

Shared Memory (SM) switches are widely used for its high throughput,low delay and efficient use of memory.This paper compares the performance of two prominent switching schemes of SM packet switches:Cell-Based Switching (CBS) and Packet-Based Switching (PBS).Theoretical analysis is carried out to draw qualitative conclusion on the memory requirement,throughput and packet delay of the two schemes.Furthermore,simulations are carried out to get quantitative results of the performance comparison under various system load,traffic patterns,and memory sizes.Simulation results show that PBS has the advantage of shorter time delay while CBS has lower memory requirement and outperforms in throughput when the memory size is limited.The comparison can be used for tradeoff between performance and complexity in switch design.     

Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching

Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As a result, a variety of techniques has been devised to hide that performance gap, from intermediate fast memories (caches) to various prefetching and memory management techniques for manipulating the data present in these caches. In this paper we propose a new memory management technique that takes advantage of access pattern information that is available at compile time by prefetching certain data elements before explicitly being requested by the CPU, as well as maintaining certain data in the local memory over a number of iterations. In order to better take advantage of the locality of reference present in loop structures, our technique also uses a new approach to memory by partitioning it and reducing execution to each partition, so that information is reused at much smaller time intervals than if execution followed the usual pattern. These combined approaches—using a new set of memory instructions as well as partitioning the memory—lead to improvements in total execution time of approximately 25% over existing methods.     

Nonvolatile Charge Injection Memory Based on Black Phosphorous 2D Nanosheets for Charge Trapping and Active Channel Layers

2D van der Waals atomic crystal materials have great potential for use in future nanoscale electronic and optoelectronic applications owing to their unique properties such as a tunable energy band gap according to their thickness or number of layers. Recently, black phosphorous (BP) has attracted significant interest because it is a single‐component material like graphene and has high mobility, a direct band gap, and exhibits ambipolar transition behavior. This study reports on a charge injection memory field‐effect transistor on a glass substrate, where few‐layer BPs act as the active channel and charge trapping layers, and Al₂O₃ films grown by atomic layer deposition act as the tunneling and blocking layers. Because of the ambipolar properties of BP nanosheets, both electrons and holes are involved in the charge trapping process, resulting in bilateral threshold voltage shifts with a large memory window of 22 V. Finally, a memory circuit of a resistive‐load inverter is implemented that converts analog signals (current) to digital signals (voltage). Such a memory inverter also shows a clear memory window and distinct memory on/off switching characteristics.     

A new buffer management scheme for hierarchical shared memoryswitches

We study a multistage hierarchical asynchronous transfer mode (ATM) switch in which each switching element has its own local cell buffer memory that is shared among all its output ports. We propose a novel buffer management technique called delayed pushout that combines a pushout mechanism (for sharing memory efficiently among queues within the same switching element) and a backpressure mechanism (for sharing memory across switch stages). The backpressure component has a threshold to restrict the amount of sharing between stages. A synergy emerges when pushout, backpressure, and this threshold are all employed together. Using a computer simulation of the switch under symmetric but bursty traffic, we study delayed pushout as well as several simpler pushout and backpressure schemes under a wide range of loads. At every load level, we find that the delayed pushout scheme has a lower cell loss rate than its competitors. Finally, we show how delayed pushout can be extended to share buffer space between traffic classes with different space priorities     

Reliability analysis and design of a fault-tolerant random access memory system

The design of a modular RAM system which is organized in a number of memory cards is examined. Two important factors are taken into account: the size of the memory chips used in a particular memory design, and the number of memory partitions which gives the maximum memory system reliability. Expressions are derived for three memory designs using two extreme failure models for the memory chips. These provide upper and lower bounds for the card and the entire memory system reliability, and allow the selection of an optimal configuration for a memory system which has a specified capacity and word length with (1) SEC or (2) SED-DED codes with spare memory cards.     

基于硬件的内存trace工具 ——MTT的设计与实现

 本文提出了一种全新的获得访存trace的方式,并设计实现了基于硬件的零开销多平台实时访存Trace工具——MTT(Memory Trace Tool).详细介绍了MTT在采样配置、地址识别、trace输出等方面的设计细节,以及接收端配合MTT高效接收分析trace的流程,实现了一个通过MTT获得程序访存trace的完整方案.相比已有方法,MTT具有许多特点:(1)对程序透明;(2)零开销,无内存污染问题;(3)实时获取完整的全系统访存Trace;(4)可实时配置的多种在线Trace分析手段;(5)具有操作系统平台无关性.     

Electrically reprogrammable ROM using N-channel memory transistors with floating gate

An electrically reprogrammable read-only-memory (REPROM) device, providing the fully decoded and on-board-writable functions, is described. The device consists of novel N-channel memory transistors with floating gate, non-volatile memory transistors, which enable electrically reprogramming operation. The memory transistor has been through more than 10⁷ rewrite cycles with no gain facto (β) decrease. The memory device has been processed by the flat-MOS and the Si-gate technologies. It has a 2048 bit memory capacity, organized as 256 words of 8 bits. The polycrystalline silicon floating gate is covered with vapor-deposited silicon nitride. This allows selective write and erase operation, giving the memory device a new bit-level reprogrammable function.     

Poly-Si Thin-Film Transistor Nonvolatile Memory Using Ge Nanocrystals as a Charge Trapping Layer Deposited by the Low-Pressure Chemical Vapor Deposition

We have successfully developed and fabricated a poly-Si thin-film transistor (poly-Si TFT) nonvolatile memory using Ge nanocrystals (Ge-NCs) as a charge trapping layer. Process compatibility and memory operation of the device were investigated. The Ge-NC trapping layer was directly deposited by low-pressure chemical vapor deposition at 370 $^{circ}hbox{C}$. Results show that the new poly-Si TFT nonvolatile Ge-NC memory has good programming/erasing efficiency, long charge retention time, and good endurance characteristics. These results show that poly-Si TFT nonvolatile Ge-NC memory is the promising nonvolatile memory candidate for system-on-panel application in the future.      

A Flexible Programmable Memory BIST for Embedded Single‐Port Memory and Dual‐Port Memory

Programmable memory built‐in self‐test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single‐port memory and dual‐port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.     

Minimizing the required memory bandwidth in VLSI systemrealizations

In this paper, we present the problem of storage bandwidth optimization (SBO) in VLSI system realizations. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the subsequent memory allocation and assignment tasks to come up with a cheaper memory architecture with less memories and memory ports. The importance and the effect of SBO is shown on realistic examples both in the video and asynchronous transfer-mode (ATM) domains. We show that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous memory accesses. Our problem formulation leads to the optimization of a conflict (hyper) graph. For the target domain of ATM, only flat graphs without loops have to be treated. For this subproblem, a prototype tool has been implemented to demonstrate the feasibility of automating this important system design step     

Design of a transmission gate based CMOL memory array

A design of a nanoelectronic memory array, compatible with both the molecular switch (nanodevice) electrical characteristics and CMOS 45 nm semiconductor technology node is presented. The proposed transmission gate based CMOL (hybrid CMOS/MOLecular) memory cell does not suffer from the operational difficulties faced by the conventional CMOL cell. The control circuitry with improved multiplexer designs is introduced, and it shows that the required voltage levels to program the nanodevices can be achieved. Moreover, the proposed memory cell has the same area as the existing CMOL inverter cell allowing easier implementation of both logic and memory circuits on the same chip.