基于HEVC的CABAC二进制算术编码器的FPGA实现

本文基于H.265/HEVC视频编码标准,实现了CABAC编码中二进制算术编码器常规编码模式下的一种硬件流水线结构,根据算法特性设计并优化了编码器的硬件架构,将概率状态数据储存在SRAM中,并使用查找表优化概率估计更新运算;对编码数据进行打包处理,简化概率估计更新带来的计算,以优化视频数据流编码速度;二进制算术编码采用多级流水线结构,支持四路并行编码.仿真结果表明,本文的硬件CABAC二进制算术编码器平均每时钟周期可以完成4个bin的编码,符合较高帧率的1080p视频实时编码要求.     

JPEG2000中高速Tier1编码器的VLSI设计

提出并实现了一种用于JPEG2000编码芯片中高速Tier1编码器的并行流水结构。该编码器采用了双位平面并行编码、通道扫描的流水控制、状态变量实时产生电路以及列内并行上下文生成等技术,实现了一种0状态存储器的多并行流水位平面编码器;并行同步流水的多记号输入算术编码器以及不定算术编码周期下的多输入同步读取电路,使算术编码速度平均为1.3上下文编码记号对/时钟;对算术编码产生的压缩码流存储呈高效的宏流水线结构。该编码器在100MHz工作时钟下,最高编码速度为85M小波系数/s。用SMIC0.25μm工艺库综合时,门电路为6.3万门,片上存储器为26kb(码块大小32×32),关键路径为5.2ns。     

CMMB标准中RS编码的FPGA实现

简要介绍了移动电视传输标准CMMB中RS(里德-索罗门)编码的特点.采用Matlab进行算法验证,并用FPGA实现.字节交织使用乒乓流水线结构,缩短了等待时间.针对k=176设计出节约成本的编码器.提出利用VGA接口获取FPGA验证数据源,使用"编码-解码-重现"的模式对RS编码器充分验证.     

JPEG2000中算术编码的VLSI结构设计

算术编码算法对于无损数据压缩是一种非常有效的方法,它已经被JPEG2000标准所采用.通过研究JPEG2000标准中的算术编码算法,设计了一种算术编码器的VLSI结构.该设计用Verilog语言进行了RTL级描述,然后用Modelsira对电路进行了仿真,经Quartus综合以后在FPGA上进行了验证.实验表明,在Ahera的芯片EP2C35F672C8上,该设计最高工作时钟可达63.37 MHz,可以作为IP核应用于JPEG2000图像编码芯片中.     

JPEG2000标准中MQ编码器的VLSI结构设计

MQ编码器是JPEG 2000标准中重要的无损压缩算法,可获得很高的压缩效率.但因其算法复杂度高,执行速度慢,使其应用受到很大限制.为了获得高速处理能力,设计一种高速MQ编码器的VLSI结构,采用三级流水线结构,对算法进行优化,并改进概率估计表内容.设计使用Verilog进行编程,最后通过Modelsim 6.1进行仿真.实验结果表明,该设计极大地提高了编码速度.这里的研究对于JPEG 2000在实际中的应用有着重要的意义.     

高速光网络系统中FEC编码器的设计与实现

给出了高速光网络系统中FEC编码器的设计方案与实现手段,详细介绍了RS码的编码原理、有限域算术实现及FEC编码器的硬件实现方法.     

一种新型的样本并行JPEG2000编码器EB COT体系

提出了一种新型的用于JPEG2000的、基于样本并行(sample-parallel)的低时钟数EBCOT编码器体系,有效降低了处理时间.体系包括1个每周期完成4个样本编码的位平面编码器,和3个每周期完成2位比特编码的内容自适应二进制算术编码器.其中的位平面编码器在码通并行(pass-parallel)的基础上进一步并行了每列4位样本的编码操作.二进制算术编码器通过采用流水线技术来匹配位平面编码器的高吞吐量.     

卷积码编码及其Viterbi译码算法的FPGA实现

探讨了卷积码编码及其Viterbi译码算法的FPGA（Field-Programmable GateArray）实现,根据编码器的结构,分别采用了有限状态机转换的编码法和基于流水线结构的状态转换译码法,有效地提高了编译码的速度.最后给出了（2,1,2）卷积码的编码及其Viterbi译码算法的实验仿真结果。     

一种基于EZW的ROI图像联合压缩加密算法

提出一种基于EZW编码的ROI图像联合压缩加密算法,阐述了上下文修正和判决修正的原理及实现,对所提出算法的安全性进行了评估。对算法进行仿真,结果表明相对于原始图像压缩算法,该算法的重构图像基本具有相同的压缩效率;相较于提升系数的ROI方法,该算法采用小波域图像分割,不需要对ROI形状信息进行编码,并可灵活调整ROI与背景区域(BG)的重构质量;相较于区间分裂算术编码器而言,该算法采用自适应算术编码,可获得更好的安全性;结合比特平面编码技术,使用不同密钥对ROI不同小波分辨力的系数分别加密,实现分辨力选择性加密,以满足不同应用需求。     

基于JPEG2000的二进制算术编码的FPGA实现方案

本文提出了一种实用的MQ算术编码器的FPGA(Field-Programmable Gate Array,现场可编程门阵列)硬件实现方案,并对MQ算术编码器的原理进行了分析,并介绍了基于JPEG2000标准所采用的三级流水结构的具体实施过程.     

Concurrency techniques for arithmetic coding in JPEG2000

JPEG2000 is a recently standardized image compression algorithm. The heart of this algorithm is the coding scheme known as embedded block coding with optimal truncation (EBCOT). This contributes the majority of processing time to the compression algorithm. The EBCOT scheme consists of a bit-plane coder coupled to a MQ arithmetic coder. Recent bit-plane coder architectures are capable of producing symbols at a higher rate than the existing MQ arithmetic coders can absorb. Thus, there is a requirement for a high throughput MQ arithmetic coder. We examine the existing MQ arithmetic coder architectures and develop novel techniques capable of absorbing the high symbol rate from high performance bit-plane coders, as well as providing flexible design choices.     

Arithmetic coding for data compression

Arithmetic coding provides an effective mechanism for removing redundancy in the encoding of data. We show how arithmetic coding works and describe an efficient implementation that uses table lookup as a first alternative to arithmetic operations. The reduced-precision arithmetic has a provably negligible effect on the amount of compression achieved. We can speed up the implementation further by use of parallel processing. We discuss the role of probability models and how they provide probability information to the arithmetic coder. We conclude with perspectives on the comparative advantages and disadvantages of arithmetic coding     

基于率失真优化的递进UTCQ编码

本文提出了一种基于UTCQ量化器的递进静态图像小波编码算法。一致网格编码量化(UTCQ)用于小波系数的量化并得到了非常好的量化效果。UTCQ超集索引值构成系数位平面,率失真优化按照率失真斜率递减的顺序从系数位平面选择编码系数位。最先编码的位具有最大的率失真斜率,每编码一位都会使失真减少最大。率失真斜率的计算仅仅是利用MQ自适应算术编码器的概率状态估计表而进行的查表过程。MQ算术编码器进一步压缩率失真优化选择的系数位。率失真门限方法的编码速度比搜索最大的率失真斜率更快。该算法有较快的编码速度以及好的压缩效果。     

基于人眼视觉特性加权的率失真优化编码算法

本文提出了一种基于人眼视觉特性加权的率失真优化的嵌入式静态图像编码算法。率失真优化是按照率失真斜率递减的顺序编码系数位,最先编码的位具有最大的率失真斜率,每编码一位都会使失真减少最大。率失真斜率的计算仅仅是利用MQ自适应算术编码器的概率状态估计表而进行的查表过程,率失真门限方法的编码速度比搜索最大的率失真斜率更快。基于人眼视觉特性的加权因子改变编码位序而不是编码值,该算法有更快的编码速度以及较好的压缩效果。     

JPEG2000算术编码器的改进算法与实现

作为新一代静止图像压缩标准的JPEG2000标准拥有压缩比高,支持多分辨率等优点。JPEG2000的编码方式采用了嵌入式码块编码(EBCOT)方式,在编码过程中采用了MQ算术编码。文中分析了它对内容单一、信息量少图像编解码的不足,针对这些不足提出了一种对MQ算术编码器流程的改进算法。这种算法提高了JPEG2000对简单图像压缩的PSNR值,使解码后的图像更加清晰。     

Block arithmetic coding for source compression

We introduce “Block Arithmetic Coding” (BAC), a technique for entropy coding that combines many of the advantages of ordinary stream arithmetic coding with the simplicity of block codes. The code is variable length in to fixed out (V to F), unlike Huffman coding which is fixed in to variable out (F to V). We develop two versions of the coder: 1) an optimal encoder based on dynamic programming arguments, and 2) a suboptimal heuristic based on arithmetic coding. The optimal coder is optimal over all V to F complete and proper block codes. We show that the suboptimal coder achieves compression that is within a constant of a perfect entropy coder for independent and identically distributed inputs. BAC is easily implemented, even with large codebooks, because the algorithms for coding and decoding are regular. For instance, codebooks with 2³² entries are feasible. BAC also does not suffer catastrophic failure in the presence of channel errors. Decoding errors are confined to the block in question. The encoding is in practice reasonably efficient. With i.i.d. binary inputs with P(1)=0.95 and 16 bit codes, entropy arguments indicate at most 55.8 bits can be encoded; the BAC heuristic achieves 53.0 and the optimal BAC achieves 53.5. Finally, BAC appears to be much faster than ordinary arithmetic coding     

A Scalable Architecture for MPEG-4 Wavelet Quantization

Wavelet-based image compression has been adopted in MPEG-4 for visual texture coding. All wavelet quantization schemes in MPEG-4—Single Quantization (SQ), Multiple Quantization (MQ) and Bi-level Quantization—use Embedded Zero Tree (EZT) coding followed by an adaptive arithmetic coder for the compression and quantization of a wavelet image. This paper presents the OZONE chip, a dedicated hardware coprocessor for EZT and arithmetic coding. Realized in a 0.5 m CMOS technology and operating at 32 MHz, the EZT coder is capable of processing up to 25.6 Mega pixel-bitplanes per second. This is equivalent to the lossless compression of 31.6 8-bit grayscale CIF images (352 × 288) per second. The adaptive arithmetic coder processes up to 10 Mbit per second. The combination of the performance of the EZT coder and the arithmetic coder allows the OZONE to perform visual-lossless compression of more than 30 CIF images per second. Due to its novel and scalable architecture, parallel operation of multiple OZONEs is supported. The OZONE functionality is demonstrated on a PC-based compression system.     

High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression

In state-of-the-art multimedia compression standards, arithmetic coding is widely used as a powerful entropy compression method. In the MPEG-4 standard a specific 4-symbol, multiple-context arithmetic coder is used for wavelet based image compression. In this paper we present a first-of-a-kind architecture capable of processing close to 1 symbol per cycle, managing multiple context in a simple, yet cost-efficient manner. We explain the need for such an architecture, develop the algorithm and propose an efficient implementation. The characteristics of the architecture are detailed and a comparison with other alternatives is presented. This architecture has been synthesized achieving a maximum speed of 170 MHz, equivalent to 340 Mbits/s.