Furnace nitridation of thermal SiO2 in pureN2O ambient for ULSI MOS applications

Furnace nitridation of thermal SiO₂ in pure N₂ O ambient for MOS gate dielectric application is presented. N₂O-nitrided thermal SiO₂ shows much tighter distribution in time-dependent dielectric breakdown (TDDB) characteristics than thermal oxide. MOSFETs with gate dielectric prepared by this method show improved initial performance and enhanced device reliability compared to those with thermal gate oxide. These improvements are attributed to the incorporation of a small amount of nitrogen (~1.5 at.%) at the Si-SiO₂ interface without introducing H-related species during N₂O nitridation     

Resistive switching characteristics of Sm2O3 thin films for nonvolatile memory applications

This study investigates a sputtered Sm₂O₃ thin film to apply into a resistive random access memory device. The proposed device exhibits a stable resistance ratio of about 2.5 orders after 10⁴ cycling bias pulses and no degradation for retention characteristics monitored after an endurance test at 85 °C. The conduction mechanisms for low and high resistance states are dominated by ohmic behavior and trap-controlled space-charge limited current, respectively. The resistance switching is ascribed to the formation/rupture of conductive filaments.     

Electrical and interfacial characteristics of nanolaminate (Al2O3/ZrO2/Al2O3) gate stack on fully depleted SiGe-on-insulator

The structural and electrical characteristics of a novel nanolaminate Al₂O₃/ZrO₂/Al₂O₃ high-k gate stack together with the interfacial layer (IL) formed on SiGe-on-insulator (SGOI) substrate have been investigated. A clear layered Al₂O₃ (2.5 nm)/ZrO₂ (4.5 nm)/Al₂O₃ (2.5 nm) structure and an IL (2.5 nm) are observed by high-resolution transmission electron microscopy. X-ray photoelectron spectroscopy measurements indicate that the IL contains Al-silicate without Ge atom incorporation. A well-behaved C–V behavior with no hysteresis shows the absence of Ge pileup or Ge segregation at the gate stack/SiGe interface.     

Characterization of the annealing impact on La2O3/HfO2 and HfO2/La2O3 stacks for MOS applications

The impact of various rapid thermal annealing used during the integration on the La₂O₃/HfO₂ and HfO₂/La₂O₃ stacks deposited by Atomic Layer deposition was analyzed. The consequences of lanthanum localization in such stacks on the evolution of the films during the rapid thermal annealing are investigated in term of morphology, crystalline structure, silicate formation and film homogeneity as a function of the depth. It appeared that the La₂O₃ location has an impact on the temperature of the quadratic phase formation which could be linked to the formation of SiOHfLa silicate and the resistance of the films to dissolution in HF 0.05 wt%.     

High-k HfO2-Ta2O5 mixed layers: Electrical characteristics and mechanisms of conductivity

Electrical properties of mixed HfO₂-Ta₂O₅ films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO₂ addition to the Ta₂O₅ is thickness dependent and the thicker layers exhibit advantages over the pure Ta₂O₅ (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO₂ and Ta₂O₅ mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta₂O₅-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO₂-Ta₂O₅ stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Electrical properties of CuInSe2 single crystals

Various bulk electrical properties and device characteristics have been measured. It has been shown that the majority carrier type is dependent on crystal stoichiometry. Mobilities of 660 cm²/V sec and 30 cm²/V sec have been measured for n-and p-type samples, respectively. Rectifying contacts and p-n junctions have been investigated by small signal analysis and the associated doping levels and equilibrium band diagrams have been determined. Photovoltage measurements on rectifying contacts have shown that the band-gap has a value of 0.95 ± 0.01eV.     

Electrical and optical properties of AgInS2

Crystal sizes of AgInS₂ grown by a directional freezing depend on sulphur pressures at the preparation. The conductivity is only n-type and nominally undoped AgInS₂ has the resistivity of 25 Ω-cm and the Hall mobility of 64 cm²/V sec. Sulphur vacancies of AgInS₂ become electron-trapping levels in the forbidden band. It is obtained from the measurements of thermally stimulated current that the levels lie at E_T1 = 0·19±0·01 eV and E_T2 = 0·40±0·01 eV, and the concentrations depend on sulphur pressures at the crystal preparations. AuAgInS₂ contacts operate as a Schottky barrier diode and the barrier height is 0·97 eV. AgInS₂ has a dichroism because of its uniaxial lattice structure. The transition is direct for $\text{E}\text{⊥c}$ and indirect for $\text{E}\text{∥c}$, and the values for the energy gap are E_g^⊥ = 1·88±0·01 eV and E_g^∥ = 1·77±0·01 eV, respectively.     

氮气或氧气气氛退火的氧化铪材料电荷泄漏情况研究

本文中, 使用开尔文探针显微镜,研究了不同退火气氛(氧气或氮气)情况下氧化铪材料的电子和空穴的电荷保持特性。与氮气退火器件相比,氧气退火可以使保持性能变好。横向扩散和纵向泄露在电荷泄露机制中都起了重要的作用。 并且,保持性能的改善与陷阱能级深度有关。氮气和氧气退火情况下,氧化铪存储结构的的电子分别为0.44 eV, 0.49 eV,空穴能级分别为0.34 eV, 0.36 eV。 最后得到,不同退火气氛存储器件的电学性能也与KFM结果一致。对于氧化铪作为存储层的存储器件而言,对存储特性的定性和定量分析,陷阱能级,还有泄漏机制研究是十分有意义的。     

Electrical switching in single crystal VO2

I–V characteristics of single crystal vanadium dioxide has been measured using a constant current source in the ambient temperature region 220–325°K. The temperature of the crystal surface has also been measured. It is observed that the switching voltage (V_th) increases but the current at switching (I_th) decreases with decreasing temperature, giving a temperature independent threshold power (V_th × I_th). At switching, the temperature of the crystal surface increases only by 3–6°K above ambient for different ambient temperatures. These results can be qualitatively explained by assuming that a filament (channel) is formed before switching. The switching occurs when the temperature of this filament of finite width approaches the semiconductor-metal transition temperature. The initial width of the channel at switching decreases with decreasing temperature and at a given ambient temperature the channel width increases with increasing current in the post breakdown region.     

纯铜表面激光熔覆TiB2/Cu涂层的组织及导电性能

为了满足电磁导轨的使用要求,采用激光熔覆技术在纯铜表面通过预置粉的方式制备了不同成分TiB2/Cu涂层,用光学显微镜、扫描电镜和X射线衍射分析了涂层的微观结构及相组成。涂层由Cu和TiB2两相组成,当TiB2的质量分数分别为0.02,0.05和0.1时,涂层的显微硬度分别约为95HV0.1,105HV0.1和152HV0.1,电导率为22.9MS/m,20.4MS/m和16.4MS/m。涂层与基体呈良好冶金结合,无裂纹在,TiB2颗粒存在团聚现象,熔覆层组织为外延生长的柱状晶。结果表明,随着TiB2的含量增大,涂层显微硬度升高,涂层的电导率下降。     

Electrical characterisation and reliability of HfO2 and Al2O3–HfO2 MIM capacitors

Current leakage and breakdown of MIM capacitors using HfO₂ and Al₂O₃–HfO₂ stacked layers were studied. Conduction in devices based upon HfO₂ layers thinner than 8 nm is probably dominated by tunnelling. Al₂O₃–HfO₂ stacked layers provide a limited benefit only in term of breakdown field. Constant-voltage wear-out of samples using insulating layer thicker than 6 nm is dominated by a very fast increase of the leakage current. A two step mechanism involving the generation of a conduction path followed by a destructive thermal effect is proposed to explain breakdown mechanism.     

Electrical Characterization of ZrO2/Si Interface Properties in MOSFETs With ZrO2 Gate Dielectrics

MOSFETs incorporating ZrO₂ gate dielectrics were fabricated. The I_DS-V_DS, I_DS-V_GS , and gated diode characteristics were analyzed to investigate the ZrO₂/Si interface properties. The interface trap density (D _it) was determined to be about 7.4times10¹² cm ^-2middoteV^-1 using subthreshold swing measurement. The surface-recombination velocity (s₀) and the minority carrier lifetime in the field-induced depletion region (tau _0,FIJ) measured from the gated diodes were about 3.5times10 ³ cm/s and 2.6times10^-6 s, respectively. The effective capture cross section of surface state (sigma_s) was determined to be about 5.8times10^-16 cm² using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxides was also made     

Electrical properties of MOSFET's with N2O-nitridedLPCVD SiO2 gate dielectrics

Electrical properties of MOSFETs with gate dielectrics of low-pressure chemical-vapor-deposited (LPCVD) SiO₂ nitrided in N₂O ambient are compared to those with control thermal gate oxide. N₂O nitridation of CVD oxide, combines the advantages of interfacial oxynitride growth and the defectless nature of CVD oxide. As a result, devices with N₂O-nitrided CVD oxide show considerably enhanced performance (higher effective electron mobility), improved reliability (reduced charge trapping, interface state generation, and transconductance degradation), and better time-dependent dielectric breakdown (TDDB) properties (t_BD ) compared to devices with control thermal oxide     

Improved electrical properties using SrTiO3/Y2O3 bilayer dielectrics for MIM capacitor applications

In this paper, we show that the capacitance–voltage linearity of MIM structures can be enhanced using SrTiO₃ (STO)/Y₂O₃ dielectric bilayers. The C(V) linearity is significantly improved by combining two dielectric materials with opposite permittivity-voltage responses. Three STO/Y₂O₃ stacks with different thicknesses were realized and compared to a 20 nm STO single layer structure. We observed that an increase in the Y₂O₃ thickness leads to an improvement in the voltage linearity, while maintaining an overall capacitance density greater than 10 fF/μm².     

On the reliability of ZrO2 films for VLSI applications

In this paper we present a systematic investigation of the effects of electrical stress on reliability of zirconium oxide films. In particular, we monitored stress-induced leakage current, high-field conduction and capacitance curves as function of the applied voltage and the injected charge. Defect density in the bulk oxide have been extracted from measurements by means of literature models. As a result, a square root time dependence of the stress-induced defects has been found.     

Electrical stress and plasma-induced traps in SiO2

High field stress and N₂ reactive ion etching (RIE)-mode plasma-generated positive oxide charge in thin (13 nm) SiO₂–Si structures have been studied. A threshold field of about 8.5–9 MV/cm for positive charge formation is found. It is established that both high field stress and RIE-like plasma treatment create nonuniformly distributed positive charge in the depth of the oxide, in the form of bulk traps and slow states. It is found that the generation of neutral bulk traps is an attribute, only of the high field stressing. The structural nature of the process-induced traps is discussed. It is suggested that the impact ionization of oxygen vacancies accounts for the positive charge and neutral trap creation.     

Electrical measurements of voltage stressed Al2O3/GaAs MOSFET

Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al₂O₃ gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current (I_g) on the gate voltage (V_g) was found to fit the CVS data of the low positive V_g range. The percolation model well explains the degradation of I_g after a high positive V_g stress. A positive threshold voltage (V_th) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al₂O₃ layer during the initial CVS, while the trapping of electrons by existing traps in the Al₂O₃ layer is responsible for the V_th shift during the subsequent CVS.     

Electrical properties of ultrathin oxide grown by high pressure oxidation and N2O nitridation for ULSI device applications

For the first time, the feasibility of ultrathin oxides grown by high pressure oxidation (HIPOX) technology in O₂ ambient and nitrided in N₂O ambient with rapid thermal processing has been investigated in order for them to be used as a gate oxide of ULSI devices. The dielectric breakdown electric field (E _BR) and the midgap interface trap density (D _itm) of the nitrided-HIPOX oxide are ?13:9MVcm^?1 and 2 × 10¹⁰cm^?2eV^?1 respectively which are almost the same as those of the control oxide and the nitrided-control oxide. The time-tobreakdown (t_BD) of the nitrided-HIPOX oxide is longer than that of the control oxide at low electric field (<10^?4 A cm^?2) owing to the combination of nitrogen and defects near the Si?SiO₂ interface during nitridation. The lifetimes of the nitrided-HIPOX oxides increase initially, reaching a maximum value of 1:2 × 10⁹ s at a stress current density of 1 × 10^?6 A cm^?2,corresponding to over 10 years, and then decrease as nitridation proceeds.