A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.     

A self-timed divider using a new fast and robust pipeline scheme

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)     

An efficient self-timed adder realized using conventional CMOS standard cells

Usually, efficient self-timed adders are realized using the dynamic differential cascode voltage switch logic. This allows the end-completion to be easily detected, but it makes circuit design and testing very complex, compelling the production of full-custom layouts and leading to a very long time before marketing. This paper presents a new 56-bit high-speed self-timed adder realized with conventional AMS 0.35 μm CMOS standard cells. The proposed circuit uses overlapped execution circuits, which exploit the initialization time that always elapses between two consecutive addition operations. Compared to several self-timed adders existing in the literature, the addition circuit proposed here shows brilliant advantages in terms of speed-performance, silicon area occupancy and power dissipation.     

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

A new logic style called low-swing current mode logic (LSCML) is presented. It features a dynamic and differential structure and a low-swing current mode operation. The LSCML logic style may be used for hardware implementation of secure smart cards against differential power analysis (DPA) attacks but also for implementation of self-timed circuits thanks to its self-timed operation. Electrical simulations of the Khazad S-box have been carried out in 0.13 μm PD (partially depleted) SOI CMOS technology. For comparison purpose, the Khazad S-box was implemented with the LSCML logic and two other dynamic differential logic styles previously reported. Simulation results have shown an improved reduction of the data-dependent power signature when using LSCML circuits. Indeed the LSCML based Khazad S-box has shown a power consumption standard deviation more than two times smaller than the one in DyCML and almost two times smaller than the one in DDCVSL.     

Clock-delayed domino for dynamic circuit design

Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is as easy to design with as static CMOS circuits from a logic design and synthesis perspective. Design tools developed for static CMOS are used as part of a methodology for automating the design of CD domino circuits. The methodology and CD domino's characteristics are demonstrated in the design of a 32-b carry look-ahead adder. The adder was fabricated with MOSIS's 0.8-μm CMOS process with scalable CMOS design rules that allow a 1.0-μm drawn gate length. Measurements of the adder show a worst case addition of 2.1 ns. The CD domino adder is 1.6× faster than a dual-rail domino adder designed with the same cell library and technology     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

In this paper, a new leading-zero counter (or detector) is presented. New boolean relations for the bits of the leading-zero count are derived that allow their computation to be performed using standard carry-lookahead techniques. Using the proposed approach various design choices can be explored and different circuit topologies can be derived for the design of the leading-zero counting unit. The new circuits can be efficiently implemented either in static or in dynamic logic and require significantly less energy per operation compared to the already known architectures. The integration of the proposed leading-zero counter with the leading-zero anticipation logic is analyzed and the most efficient combination is identified. Finally, a simple yet efficient technique for handling the error of the leading-zero anticipation logic is also presented. The energy-delay behavior of the proposed circuits has been investigated using static and dynamic CMOS implementations in a 130-nm CMOS technology.     

A scannable pulse-to-static conversion register array forself-timed circuits

This paper describes the design and hardware results of a scannable pulse-to-static conversion register array for self-timed circuits. The circuits include a self-timed control circuit and a 64-bit register array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control block allows it to require only one system clock input. The evaluation, reset, and write-enable controls are all generated within the control macro. The register array is a level-sensitive scan design, which is compatible and complies with SRCMOS test modes. This type of register array can facilitate the synchronous/asynchronous interfaces, pipelined operation, power management, and testing of advanced digital systems employing a mixture of static and dynamic circuits to achieve low power and high performance     

Design and application of pipelined dynamic CMOS ternary logic andsimple ternary differential logic

Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2-μm CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown     

On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.     

Efficient design of gallium arsenide Muller-C element

A Muller-C element is a fundamental building block of a handshake path in self-timed digital circuits. It is a basic event driven logic (EDL) gate, implementing the AND function for events. The authors present a new, improved design of the Muller-C element using GaAs MESFET technology. A static Muller-C gate is implemented that incorporates modifications of newly introduced, GaAs pseudodynamic latched logic family (PDLL) primitives. The circuit is characterised by very high speed and low power dissipation     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

All-N-logic high-speed true-single-phase dynamic CMOS logic

In this paper, a novel all-N-logic single-phase high speed dynamic CMOS logic is introduced and analyzed. The circuits achieve high speed by eliminating the need for the low-speed P-logic blocks. The use of all-N-logic allows the speed of the proposed circuits to be two to three times the speed of conventional CMOS dynamic circuits. An 2:1 frequency divider, using proposed ANL2 circuits, is simulated using 0.8 μm CMOS technology with the operating clock frequency reaching as high as 1.5 GHz. A pipelined 8-b carry generator of five-stacked NMOS transistors, which operates at a clock rate of over 710 MHz, has also been simulated. Experimental results show that the proposed circuits operate over 910 MHz implemented in a 1.2 μm CMOS technology     

Charge recycling differential logic (CRDL) for low powerapplication

A novel logic family, called charge recycling differential logic (CRDL), has been proposed and analyzed. CRDL reduces power consumption by utilizing a charge recycling technique with the speed comparable to those of conventional dynamic logic circuits. It has an additional benefit of improved noise margin due to inherently static operation. The noise margin problem of true single-phase-clock latch (TSPC) is also eliminated when a CRDL logic circuit is connected to it. Two swing-suppressed-input latches (SSILs), which are introduced for use with CRDL, have better performance than the conventional transmission gate latch. Moreover, a pipeline configuration with CRDL in a true two-phase clocking scheme shows completely race-free operation with no constraints on logic composition. Eight-bit Manchester carry chains and full adders were fabricated using a 0.8 μm single-poly double-metal n-well CMOS technology to verify the relative performance of the proposed logic family. The measurement results indicate that about 16-48% improvements in power-delay product are obtained compared with differential cascode voltage switch (DCVS) logic     

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for     

Dynamic asynchronous logic for high-speed CMOS systems

As transistor switching speed improves, synchronizing a global clock increasingly degrades system performance. Therefore, self-timed asynchronous logic becomes potentially faster than synchronous logic. To do so, however, it must exploit the techniques used in fast synchronous designs, including redundant logic, inverting logic, transistor size optimization, dynamic logic, and phase alignment. Most techniques can be applied equally well to asynchronous logic-indeed phase alignment is easier-but combining dynamic and asynchronous logic is more difficult. Minimum refresh intervals together with race- and hazard-free operation must be guaranteed. An initial chip implementation that combines dynamic and asynchronous logic running at 500 MHz in 2-μm CMOS is described. With the addition of transistor size optimization, simulations show the same circuit running in the same technology at 800 MHz     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A New Static Differential CMOS Logic with Superior Low Power Performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.Muhammad E.S. Elrabaa received his B.Sc. degree in computer Engineering from Kuwait University, Kuwait in 1989, and his M.A.Sc. and PhD degrees in Electrical Engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1995, respectively. His graduate research dealt with Digital BiCMOS ICs and Low-Power circuit techniques. From 1995 till 1998, he worked as a senior circuit designer with Intel Corp., in Portland, Oregon, USA. He designed and developed low power digital circuits for Microprocessors. From 1998 till 2001 he was with the EE department, UAE University as an assistant professor. In 2001, he joined the computer Engineering department, KFUPM University. His current research interests include reconfigurable computing, low-power circuits, and communication circuits. He authored and co-authored several papers, a book and holds two US patents.     

Adiabatic pseudo-domino logic

A new logic structure, adiabatic pseudo-domino logic (APDL), which is the combination of adiabatic theory and CMOS domino logic is described. APDL circuits are compact, easy to cascade, and have outputs that are more stable than other adiabatic logic. Comprehensive circuit simulations show that APDL logic can recover over 80% of the energy dissipated in conventional static CMOS logic     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.