基于DSP验证平台的MP3解码算法研究与实现

本文针对基于16位定点DSP核的MP3解码算法研究及实现,提出了针对DSP芯片特点的软硬件优化设计方法,包括高级语言算法的结构优化和汇编语言的软硬件优化.在DSP验证平台上进行128Kbps,44.1KHz的立体声MP3解码,优化后运算量为46.6MIPS,程序空间为20.4Kbyte,优化率分别达到65.6%和49.6%.实验结果表明音频算法和DSP结构软硬件协同设计的重要性.     

基于DSP验证平台的MP3解码算法研究与实现

本文针对基于16位定点DSP核的MP3解码算法研究及实现,提出了针对DSP芯片特点的软硬件优化设计方法,包括高级语言算法的结构优化和汇编语言的软硬件优化.在DSP验证平台上进行128Kbps,44.1KHz的立体声MP3解码,优化后运算量为46.6MIPS,程序空间为20.4Kbyte,优化率分别达到65.6%和49.6%.实验结果表明音频算法和DSP结构软硬件协同设计的重要性.     

MP3音频解码速度优化

MP3采用MPEG-1 LayerIII层标准压缩编码格式,压缩率很高,失真也较小,算法也较为复杂.就MP3解码过程中,针对各解码模块的特点,通过浮点转定点运算、分段拟合、查找表等方法,对解码复杂度较高的模块进行算法优化,并且在16位定点DSP芯片实现,优化后解码每帧音频格式的指令数降到最初的1/ 20.     

基于DSP的MP3实时解码系统的设计与实现

介绍了一种基于定点DSP的MP3解码系统的设计与实现。系统以高性能的定点DSPTMS320vc5416为核心处理器,通过对DSP的软件编程实现对MP3数据实时解码。     

MP3编码量化模块的改进

MP3是应用最广泛的一种音频格式,MP3解码芯片已发展成熟,却很少有实时编码器产品。这是因为MP3编码算法的运算量远大于解码算法,而量化模块在编码算法中占很大的比重(38．2％),为实现便携式设备的MP3实时编码,有必要对量化模块进行改进来降低运算复杂度。在分析了现有的一些改进方法后,提出了在外循环中限制量化频带以滤去高频信号,计算比例因子初值以减少循环次数;内层循环中计算量化因子初值后自适应调整步长的方法。在获得良好音频质量的同时将量化模块运算量减少到标准算法的6％,使得整个编码算法的运算量降低到标准算法的64％,配合简化声学心理模型和分析滤波器组快速算法,可在单片DSP或ARM上实现MP3实时编码。     

ADPCM语音编解码电路设计及FPGA实现

近年来，多媒体技术逐渐深入到人们的生活中。MP3播放器已经成为流行的便携式音频播放设备，由于MP3编码算法非常复杂，目前，一部分MP3播放器的录音功能主要基于ADPCM算法和DSP来实现。本文阐述了ADPCM语音编解码VLSI芯片的设计方法以及利用FPGA的硬件实现。     

具有ADC和DAC的MP3解码器

介绍了MP3解码器的特性、工作原理和应用电路。针对MP3解码器高精度和低功耗的技术要求，在片内使用一个新型32位浮点DSP核和高效率电源管理技术。     

卫星数字声广播信源编码CMP3和AAC的比较

最近10余年基于感知音频编码的高质量Hi-Fi音频压缩方法已取得突破，本文简要介绍感知音频编码原理，然后分别叙述MP3和MPEG－2 AAC的算法，并对高质量音频编码的主观评价方法作了介绍，给出了MP3和AAC的主观评价结果，在128kbps/2-channel时AAC的重建音质明显高于MP3，最后给出了AAC的其它特点。     

一种以VBR MP3音频为载体的隐写方法

现有的以MP3音频为载体的隐藏算法大都针对恒定码率编码(CBR)的MP3,而把动态码率编码(VBR)的MP3作为掩蔽载体的研究还比较少。与CBR相比,VBR编码技术能够使MP3音频体积更小、音质更高,这一优点使得VBR MP3在MP3音频市场中的份额越来越大。基于最低有效位方法,提出了一种针对编码参数比特率索引的VBR MP3音频隐写方法。该算法可实现盲提取,而且仅仅通过解析边信息即可提取秘密信息,而不需要对载体音频进行完全解码。实验结果表明,所提算法不仅感知性良好,同时隐藏容量不受音频风格的影响。     

基于PowerPC405的MP3实时解码系统设计与实现

文章介绍了一种在FPGA上用PowerPC405实现MP3实时解码SoC系统的方法。通过使用IP核搭建SoC硬件结构,并进行定点MP3解码软件算法移植,完成软硬件协同设计和验证,实现MP3音乐实时、高品质的解码播放。     

一款32位定点DSP电路的设计

文章通过对32位定点DSP的体系结构及其设计方法的研究,重点阐述了32位定点DSP中CPU包括ALU、MPY、ARAU、流水线、指令系统和总线接口等关键逻辑部件工作原理,对各个逻辑部件的设计思路和实现方法进行了分析描述。采用基于标准单元正向设计方法,设计了一款32位指令集的定点DSP电路,该电路采用哈佛总线结构,可以在单周期内实现16×16位有符号整数乘法、32位累加和32位数据的算术逻辑运算,处理精度高。该电路采用0.5μm 1P3M CMOS工艺流片,集成度7万门,工作频率可达36 MHz,动态功耗594 mW。     

A fast square-rooting algorithm using a digital signal processor

The computation of square roots is required in signal processing applications, such as adaptive filtering using transversal filters or lattice filters, spectral estimation, and many other fields of engineering sciences. Actually, all the existing digital signal processors (DSP) have a multiplier-accumulator. We present a simple binary algorithm for square-rooting using a processor with multiplier. Only shifts, additions, and multiplications are used and unlike the Newton-Raphson approach, divisions are not necessary. The method can also be interesting for the computation of divisions. The algorithm has been implemented in 16-bit fixed-point arithmetic on a TMS32010 DSP processor. The computational requirements are compared with the Newton-Raphson method. The fixed-point code of the algorithm written in TMS32010 Assembly language is also given.     

G.729语音压缩编码在DSP上的实现

文章主要介绍了G．729编解码器的算法原理以及它在一片TMS320VC5402定点DSP芯片上实时实现时的软硬件设计过程。     

高性能定点DSP位处理单元(BMU)设计

位处理单元(BMU)是定点数字信号处理器(DSP)中主要的运算单元。数字信号处理器要做大量的位处理的运算,因此该单元的设计极大地影响着DSP的性能。用全定制的方法设计用于定点DSP的位处理单元。该电路具有逻辑/算术移位、指数提取、归一化等功能,有效地解决了定点DSP的浮点运算功能。该BMU在CSMC 0.5μm CMOS工艺下实现,一共包含4 527个晶体管,资源消耗较少,在5 V工作电压下,工作速度达到了114 MHz,符合高性能DSP的要求。     

面向音频应用的可配置片上系统的设计与实现

基于一款通用的16位定点数字信号处理器,结合D/A转换器、A/D转换器和放大器等模拟电路模块,设计并实现了一种面向音频应用的可配置片上系统.该系统支持立体声输入输出,具有8～48 kHz之间可编程的采样频率,以及可编程的输入输出放大器增益.同时,设计使用了24位高精度Σ-Δ A/D转换器,并配有可供选择的数字滤波器.为支持不同应用,系统提供24位或16位的可编程字长调节.系统芯片工作在1.8 V电压下,芯片内各部分支持挂起或睡眠状态,有利于低功耗的便携式应用开发.介绍了部分关键功能模块的仿真、验证和测试,以及整个系统仿真模型的建立.     

Implementation of a 32 Kbit/s ADPCM Codec Using a General-Purpose Digital Signal Processor

This paper describes an implementation of a CCITT G.721 compatible 32kbit/s ADPCM codec, using a general-purpose digital signal processor FDSP-3 (MB8764). A single-channel ADPCM codec is realized by two FDSP-3 chips-one for the encoder and the other for the decoder. Meticulous programming techniques are employed to achieve exact computation of the CCITT algorithm exploiting all the available resources of the 16-bit fixed-point DSP. It is shown that the whole codec computation can be accomplished in about 2350 machine cycles. Thus, two FDSP-3 chips operating at 10 MHz machine cycle can handle the whole computation. The paper also covers the comparison of straight fixed-point format and the G.721 realization, and briefly examines the compatibility issue between these two methods.     

A 32-b RISC/DSP microprocessor with reduced complexity

This paper presents a new 32-b reduced instruction set computer/digital signal processor (RISC/DSP) architecture which can be used as a general purpose microprocessor and in parallel as a 16-/32-b fixed-point DSP. This has been achieved by using RISC design principles for the implementation of DSP functionality. A DSP unit operates in parallel to an arithmetic logic unit (ALU)/barrelshifter on the same register set. This architecture provides the fast loop processing, high data throughput, and deterministic program flow absolutely necessary in DSP applications. Besides offering a basis for general purpose and DSP processing, the RISC philosophy offers a higher degree of flexibility for the implementation of DSP algorithms and achieves higher clock frequencies compared to conventional DSP architectures. The integrated DSP unit provides instruction set support for highly specialized DSP algorithms. Subword processing optimized for DSP algorithms has been implemented to provide maximum performance for 16-b data types. While creating a unified base for both application areas, we also minimized transistor count and we reduced complexity by using a short instruction pipeline. A parallelism concept based on a varying number of instruction latency cycles made superscalar instruction execution superfluous     

Performance evaluation of the fractional wavelet filter: A low-memory image wavelet transform for multimedia sensor networks

Existing image wavelet transform techniques exceed the computational and memory resources of low-complexity wireless sensor nodes. In order to enable multimedia wireless sensors to use image wavelet transforms techniques to pre-process collected image sensor data, we introduce the fractional wavelet filter. The fractional wavelet filter computes the wavelet transform of a 256 × 256 grayscale image using only 16-bit fixed-point arithmetic on a micro-controller with less than 1.5 kbyte of RAM. We comprehensively evaluate the resource requirements (RAM, computational complexity, computing time) as well as image quality of the fractional wavelet filter. We find that the fractional wavelet transform computed with fixed-point arithmetic gives typically negligible degradations in image quality. We also find that combining the fractional wavelet filter with a customized wavelet-based image coding system achieves image compression competitive to the JPEG2000 standard.     

A 32-bit VLSI digital signal processor

A general-purpose programmable digital signal processor (DSP) has been implemented in 1.5-/spl mu/m (L/SUB eff/) NMOS technology using full-custom circuit design for high performance. The DSP has a 32-bit instruction set, 32-bit data path, and full-hardware 32-bit floating-point arithmetic. The architecture is described section by section, and an overview of the instruction set is presented. The extensive design verification process applied to the DSP is also described.