Intra-chip wireless interconnect for clock distribution implementedwith integrated antennas, receivers, and transmitters

A wireless interconnect system which transmits and receives RF signals across a chip using integrated antennas, receivers, and transmitters is proposed and demonstrated. The transmitter consists of a voltage-controlled oscillator, an output amplifier, and an antenna, while the receiver consists of an antenna, a low-noise amplifier, a frequency divider, and buffers. Using a 0.18-μm CMOS technology, each of these individual circuits is demonstrated at 15 GHz. Wireless interconnection for clock distribution is then demonstrated in two stages. First, a wireless transmitter with integrated antenna generates and broadcasts a 15-GHz global clock signal across a 5.6-mm test chip, and this signal is detected using receiving antennas. Second, a wireless clock receiver with an integrated antenna detects a 15-GHz global clock signal supplied to an on-chip transmitting antenna located 5.6 mm away from the receiver, and generates a 1.875-GHz local clock signal. This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with an integrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results     

Design methodology for synthesizing clock distribution networksexploiting nonzero localized clock skew

An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated     

基于异或门自选通的低功耗时钟树综合方案

本文介绍一种降低时钟网络功耗的方法。该方法基于电路中寄存器本身的状态值,在采用异或门进行自选通后构建时钟树结构,从而减少时钟信号额外翻转,降低芯片功耗。将该方法应用于一款基于SMIC0.18μmEflash 2p4m工艺下的非接触式智能卡芯片的物理设计。仿真结果表明,与传统时钟树综合方法相比,芯片功耗降低了10.7%。     

一种基于电压岛的片上网络低功耗设计

功耗问题一直是片上网络设计中最为关心的问题之一.基于全局异步局部同步(GALS)的电压岛(VFI)机制的引入不但提供了极大地降低片上功耗的可能,也解决了片上单时钟传输的瓶颈问题.本文改善了现有的两种电压岛划分、核映射及路由分配方法,提出了一种更优的综合解决方案,并进行了验证.仿真结果显示,本文的方案可以显著降低系统功耗,同时提高了片上网络性能.     

A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

In this paper, we propose a new three-dimensional (3-D) clock distribution network (CDN) scheme using a low temperature co-fired ceramic (LTCC) package level interposer with a planar cavity resonator to achieve extremely low jitter and skew clock delivery even in severe power supply noise environments, especially for digital chips in 3-D stacked chip packages. It is based on a uniform-phase of the standing wave at the quarter-wavelength planar cavity resonator embedded inside the LTCC interposer. Substantial suppression of the timing jitter and skew was successfully demonstrated through a series of design, fabrication, and measurement processes of test devices and packages.      

Distributed Differential Oscillators for Global Clock Networks

This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. The resonant network, combined with phase averaging of the distributed oscillator, provides high immunity to process-, voltage-, and temperature-variation-induced timing uncertainty. Measurement results from a prototype design implemented in a 0.18-$muhbox m$CMOS technology show almost an order of magnitude less jitter and power than a traditional tree-driven grid global clock distribution. On-chip measurement circuits are used to characterize the jitter on the test chip, while a simulation model is used to examine skew and higher-order resonances in the resonant clock network.     

A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators

The present paper introduces a resonant clock generation and distribution scheme that uses uniform amplitude and uniform phase standing wave oscillators in order to distribute a high-frequency clock signal with low skew, low jitter, and low power. A suitable distributed resonator for a global clock distribution that is inductively loaded transmission line generating a uniform amplitude and uniform phase standing wave is realized through detailed analysis of a standing wave on a loaded transmission line. A test chip is fabricated using 0.18-mum 6 M CMOS technology, and a cascaded distribution network is implemented for a global clock distribution with a space-filling curve. Furthermore, distributed local LC tanks are implemented as local resonant clock networks, which are composed of parasitic capacitors and small spiral inductors. The distributed local LC tanks are driven by a fine clock distributed with cascaded standing-wave oscillators and reduce the primary power in the clock distribution, which is dissipated as dynamic power in the parasitic capacitance of latches and/or flip flops. The measurement results reveal that, at 9.4 GHz, the peak-to-peak jitter is 5.2 ps and the clock skew is 0.8 ps, and the global and local distributions dissipated only 17% and 23% of CV² f power, respectively.     

一种分析高速时钟网络信号完整性的有效方法

本文基于有耗传输线模型,运用等效源理论首次分析了工作在GHz频率时时钟树电路互连系统对传输信号完整性的影响,对时钟树的'T’型结构引入三端口网络,计算结果表明这是一种有效的分析时钟树电路信号完整性的方法.     

Modeling of power supply noise in large chips using the circuit-based finite-difference time-domain method

In this paper, a multilayered on-chip power distribution network consisting of two million passive elements has been modeled using the finite-difference time-domain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating multilayered power grids. In addition, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers, and rise times have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise. Also, a method has been presented for analyzing package and board planes. Based on the methods presented, the interaction between chip and package has been discussed for capturing the resonant behavior that is otherwise absent when each section of the system is analyzed separately.     

单光子探测盖革雪崩焦平面用低抖动多相位时钟电路设计

针对单光子探测盖革雪崩焦平面读出电路应用,基于全局共享延迟锁相环和2维H型时钟树网络,该文设计一款低抖动多相位时钟电路。延迟锁相环采用8相位压控延迟链、双边沿触发型鉴相器和启动-复位模块,引入差分电荷泵结构,减小充放电流失配,降低时钟抖动。采用H时钟树结构,减小大规模电路芯片传输路径不对称引起的相位差异,确保多路分相时钟等延迟到达像素单元。采用0.18 μm CMOS工艺流片,测试结果表明,延迟锁相环锁定频率范围150～400 MHz。锁定范围内,相位噪声低于–127 dBc/Hz@1 MHz,时钟RMS抖动低于2.5 ps,静态相位误差低于65 ps。     

Exponentially tapered H-tree clock distribution networks

Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects decrease by approximately 35% the difference between the overshoots in the signal at the input of a tree. As compared to a uniform tree with the same area overhead, overshoots in the signal waveform at the source of the tree are reduced by 40%.     

Effect of parameter variations at chip and wafer level on clockskews

In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-μm technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level     

ThunderBird: a complete standard cell layout package

The generalized standard cell layout style handled by ThunderBird is characterized by horizontal rows of standard cells with pads placed around the periphery of the chip. Furthermore, macro blocks may be present on the chip. The standard cells are permitted to have varying heights. The two key components of ThunderBird are TimberWolf3.2, a standard cell placement and global routing package, and the YACR II channel router. The placement and global routing proceed over three distinct stages: (1) cell placement for minimum interconnect length, (2) insertion of feedthrough cells or location of built-in feeds, and another interconnect-length minimization; and (3) local changes in placement to reduce the number of wiring tracks required. This channel router features a 100% routing completion rate while usually routing each channel using a number of tracks equal to a density of the channel. Results on industrial circuits versus numerous automatic and manual layout methods showed that ThunderBird yielded area savings ranging from 15 to 75%     

一种加载缓冲器的有界偏差平面时钟布线算法

提出了一种加载缓冲器的有界偏差平面时钟布线方法.该方法由两步组成:第一步,由平面时钟布线生成一个时延相对平衡的平面时钟树;第二步,通过在平面时钟树的适当位置插入缓冲器,得到一个有界时钟偏差的平面时钟树.     

2.5Gb/s SDH/SONET通路终结芯片设计

设计了一种2.5Gb/s同步光纤网络SDH/SONET中通路终结处理器芯片.采用双向4路总线流水线结构,77.76MHz的系统时钟,可实时处理2.5Gb/s的SDH/SONET数据,终结处理后输出TUG-3/VTG信号.包括通道告警、信号失效检测、性能监测和通道跟踪等.支持STS-48/STM-16、4路STS-12/STM-4和4路STS-3/STM-1的处理.     

超深亚微米物理设计中天线效应的消除

分析了超深亚微米物理设计中天线效应的产生机理以及基于超深亚微米工艺阐述了计算天线比率的具体方法。同时,根据天线效应的产生机理并结合时钟树综合提出了消除天线效应的新方法。此方法通过设置合理的约束进行时钟树综合,使得天线效应对时钟延时和时钟偏斜的影响降到最低,从而对芯片时序的影响降到最低。最后结合一款芯片的物理设计,该设计采用台积电(TSMC)65 nm低功耗(LP)工艺,在布局布线中运用所述的方法进行时钟树综合并且使得时钟网络布线具有最大的优先权。此方法有效地消除了设计中存在的天线效应,并且使得天线效应对时钟树的影响降到最低以及对时序的影响降到最小。     

Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis

A 3D stacked IC is made of multiple dies possibly with heterogeneous process technologies. Therefore, the die-to-die variation between the stacked dies creates on-package variation in a 3D chip. In this paper, we analyze the effect of on-package variation on the 3D clock trees and address the problem of on-package variation aware layer embedding in 3D clock tree synthesis. The layer embedding problem is divided into two sub-problems: clock node embedding and clock edge embedding. While the clock node embedded problem has been intensively investigated by the previous 3D clock tree synthesis flows because the solution directly determines the TSV allocation, the clock edge embedding problem has not been fully addressed yet. We show in this work that a careful clock edge embedding can greatly reduce the impact of on-package variation on the 3D clock skew, thereby enhancing chip yield, and propose a two-step solution to the problem of on-package variation aware layer embedding of clock edges. Specifically, we formulate the edge embedding problem into a problem of maximizing the sharing of layers among the clock paths to minimize the impact of on-package variation globally and solve it efficiently, followed by applying a fine-grained refinement technique to balance the clock latency locally among the clock paths. From the experiments with Benchmark circuits, we confirm that compared to the results produced by the conventional on-package variation unaware layer embedding of clock edges, the proposed algorithm is able to improve the chip yield by 6.2–25.8% and 5.3–44.4% for 2-layered and 4-layered 3D designs, respectively.     

A 140 Mbit/s CMOS LSI framer chip for a broad-band ISDN localaccess system

A LSI framer chip, which provides a SONET-like time-division-multiplexed frame structure and which has been implemented in a production 2-μm CMOS technology, is described. Current samples of the chip have been tested functional to 160 Mb/s. The primary attributes presented include the circuit features used to achieve high-bit-rate operation, the level translation circuits which afford direct interfacing to ECL level clock and data signals, and the functional capabilities which lead to broad application of the chip in communications networks. Several examples of its use in a prototype broadband local access network are also described. The ship operates from a single 5-V supply, dissipates approximately 420 mW, and is packaged in a 68-pin leadless ceramic chip carrier (LCCC) package     

A monolithic light-emitting-diode display

A monolithic 5 × 7 array of planar diffused p-n junctions in GaAs1-xPx(x≃0.38) has been built for a light-emitting diode (LED) alphanumeric readout. A character formed by this readout is 0.246 cm high and 0.170 cm wide. The monolithic chip has all p-n junctions, n-contacts, p-contacts, interconnections and terminal metallurgy on the epitaxial layer which represents a departure from the conventional methods of making LED arrays, namely wire bonding discrete chips with contacts on two sides in a hybrid configuration. Each LED in the array is connected to one of the terminals arranged around the periphery of the chip and individually addressed by direct current from a driver on a silicon control chip. For each character position in a display there is one monolithic LED chip and one monolithic silicon control chip solder joined to terminals on a glass plate and interconnected by Cr-Cu-Cr lines evaporated onto the glass substrate. The display is addressed by serial information provided from an ROM which is read into a 35-stage shift register on the control chip which controls the drivers. Thus with two standard parts, any N-character display can be fabricated with considerable reduction in handling since no discrete elements or wire bonds are used.     

基于无线信号不规则性的无线传感网层次型拓扑控制算法

构建层次型拓扑结构是延长网络生存时间的有效方法。该文将拓扑构建过程分为由簇成员组成的感知层和由簇头组成的平面数据转发层,建立了基于无线信号不规则性的网络能耗模型以及节点成簇稳定性模型,提出了基于无线信号不规则性的层次型拓扑控制(WSIBTC)算法。WSIBTC算法根据节点平均有效传输距离将监测区域划分为多个子区域,由成簇稳定性和节点在簇中的位置决定最终簇头,簇头间形成平面拓扑结构,延长网络生存时间。分析和仿真结果表明由WSIBTC算法得到的网络拓扑大幅度地提升了网络生存时间。