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1.
Jitter in ring oscillators 总被引:1,自引:0,他引:1
Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit κ, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction 相似文献
2.
在无人机3D地形测绘中,作为核心模块的时间数字转换器(TDC)需要具有远距离测量能力和高测量分辨率。基于对测距系统的长续航、公里级测距能力和厘米级测量精度的综合考量,文章设计了一种用于TDC的低功耗多相位时钟生成电路。采用了伪差分环形压控振荡器,通过优化交叉耦合结构,在保证低功耗的前提下,提升了信号边缘的斜率,增强了时钟的抖动性能和对电源噪声的抑制能力。在电荷泵设计中,通过对环路带宽的考量选取了极低的偏置电流,在进一步降低功耗的同时缩小了环路滤波器的面积。基于SMIC 180 nm CMOS工艺完成了对多相时钟生成电路的设计。仿真结果表明,在400 MHz的输出频率下,环路带宽稳定在1 MHz。该电路在不同工艺角下均能达到较快的锁定速度,相位噪声为-88 dBc@1 MHz,功耗为1 mW,均方根抖动为27 ps,满足厘米级测距的精度需求。 相似文献
3.
Phase Noise and Jitter in CMOS Ring Oscillators 总被引:3,自引:0,他引:3
《Solid-State Circuits, IEEE Journal of》2006,41(8):1803-1816
A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker ($1/f$ ) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator. 相似文献
4.
《Solid-State Circuits, IEEE Journal of》2009,44(8):2138-2153
5.
Dubash N.B. Yongming Zhang Ghoshal U. Perng-Fei Yuh 《Applied Superconductivity, IEEE Transactions on》1997,7(3):3808-3811
We present a technique for linewidth measurement and phase-locking of Josephson oscillators using digital rapid single-flux-quantum (RSFQ) circuits. The oscillator consists of a resistively shunted 6 μm×6 μm Nb/AlOx/Nb Josephson tunnel junction that is integrated with RSFQ input and output circuits. A cascade of RSFQ T flip-flops is used to directly monitor the output of the Josephson oscillator. Spectral characteristics have been measured directly for oscillator frequencies ranging from 10-50 GHz. The linewidth can be reduced by over 100 times by phase-locking the oscillator to an RSFQ pulse train generated by an external sinusoidal signal. These Josephson oscillators can be used as on-chip stable high frequency clocks for RSFQ circuits 相似文献
6.
Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output latch (register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology 相似文献
7.
This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 27-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm2 相似文献
8.
9.
论述了UMC 65nm CMOS工艺实现的全定制全数字锁相环.该锁相环用于提供高速嵌入武SRAM内建自测试所需的时钟.分析了全数字锁相环的工作原理和电路架构,并给出了整个锁相环系统的电路和版图实现.编码控制振荡器是全数字锁相环中的核心电路,提出了一种改进的编码控制振荡器,具有高线性度和高精度的特点.在理论上分析了全数字锁相环系统的稳定性,并给出所采用的锁相环架构的稳定性公式.该锁相环达最高输出频率为2GHz,抖动小于1%. 相似文献
10.
Seong-Jun Song Sung Min Park Hoi-Jun Yoo 《Solid-State Circuits, IEEE Journal of》2003,38(7):1213-1219
A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply. 相似文献
11.
C. Mannino H. Rabah S. Weber C. Tanougast Y. Berviller M. Janiaut 《International Journal of Electronics》2013,100(12):843-861
This paper presents a totally digital phase locked loop (PLL) used for the recovery of a MPEG-2 decoder clock. The All Digital PLL (ADPLL) is implemented with a frequency synthesizer based on a new technique for phase shifting, avoiding the phase accumulation of ADPLL using a ring oscillator or avoiding the multiphase generation if a delay-locked loop (DLL) is used. The strongest point of the proposed configuration is the possibility of implementing as many ADPLLs as needed in a single circuit, in the limit of the circuit resources, without additional external circuit. The transfer characteristic, frequency resolution and jitter performance are computed and discussed. Then, the ADPLL resources and the ADPLL performances in term of time response and jitter are reported. 相似文献
12.
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM 总被引:1,自引:0,他引:1
Lee T.H. Donnelly K.S. Ho J.T.C. Zerbe J. Johnson M.G. Ishikawa T. 《Solid-State Circuits, IEEE Journal of》1994,29(12):1491-1496
This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2π radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface 相似文献
13.
A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l... 相似文献
14.
利用TSMC的O.18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明:在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4.7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112.3 dBe/Hz。芯片面积仅为0.6mm×O.6 mm,采用1.8 V电源供电,功耗低于90 mW。 相似文献
15.
Ryu C. Chung D. Lee C. Kim J. Bae K. Yu J. Lee S. 《Microwave and Wireless Components Letters, IEEE》2006,16(12):651-653
Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment 相似文献
16.
传统的PLL(Phase Locked Loop)电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC(Time-to-Digital Converter)的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环(Phase Locked Loop,PLL)电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要. 相似文献
17.
对1.25Gbps应用于千兆以太网的低抖动串并并串转换接收器进行了设计,应用了带有频率辅助的双环时钟数据恢复电路,FLL扩大了时钟数据恢复电路的捕捉范围。基于三态结构的鉴频鉴相从1.25Gbps非归零数据流中提取时钟信息,驱动一个三级的电流注入环形振荡器产生1.25GHz的低抖动时钟。从低抖动考虑引入了均衡器。该串并并串转换接收器采用TSMC0.35μm2P3M3.3V/5V混合信号CMOS技术工艺。测试结果表明了输出并行数据有较好的低抖动性能:1σ随机抖动(RJ)为7.3ps,全部抖动(TJ)为58mUI。 相似文献
18.
We report the first definitive PM and AM noise measurements at 100 GHz of indium phosphide (InP) amplifiers operating at 5 K, 77 K, and room temperature. Amplifier gain ranged from +7 to +30 dB, depending on input RF power levels and operating bias current and gate voltages. The measurement system, calibration procedure, and amplifier configuration are described along with strategies for reducing the measurement system noise floor in order to accurately make these measurements. We compute amplifier noise figure with an ideal oscillator signal applied and, based on the PM noise measurements, obtain NF=0.8 dB, or a noise temperature of 59 K. Measurement uncertainty is estimated at /spl plusmn/0.3 dB. Results show that the use of the amplifier with an ideal 100-GHz reference oscillator would set a lower limit on rms clock jitter of 44.2 fs in a 20-ps sampling interval if the power into the amplifier were -31.6 dBm. For comparison, clock jitter is 16 fs with a commercial room-temperature amplifier operating in saturation with an input power of -6.4 dBm. 相似文献
19.
《Circuits and Devices Magazine, IEEE》2006,22(6):31-38
The random jitter performance of clock, oscillator, and timing circuits can be predicted by using steady-state circuit simulation techniques that determine phase noise by analyzing the impact on phase due to thermal, flicker, channel, and shot noise present in the electronic devices. Given the phase noise response, and the steady-state operating conditions of the circuit, a wide variety of jitter measurements can be computed. Each involves a transformation of the phase noise results, with accuracy hinging on the quality of the phase noise response over a suitable range of offset frequencies 相似文献
20.
《Solid-State Circuits, IEEE Journal of》2009,44(3):797-807