A blackboard-based process planning system for the surface mount manufacture of PCBs

This paper describes a real-time computer-aided process planning (CAPP) system for printed circuit board (PCB) assembly using surface mount technology. The prototype, dynamic, realtime CAPP system described uses a blackboard to integrate multiple knowledge sources (knowledge bases) in implementing the process planning procedure. The CAPP system is implemented using the expert system environment (ESE) and structured query language (SQL). The system uses two subsystems (knowledge bases). They are a planning subsystem which performs the static process planning task and a dynamic information processing subsystem which considers the real-time changes on the shop floor and routes the PCB assembly flow. The integrated system developed generates process plans that can be implemented in real time. The use of the blackboard concept for CAPP architecture is unique and well suited for this task.     

A particle swarm optimization approach to optimize component placement in printed circuit board assembly

The particle swarm optimization (PSO) approach has been successfully applied in continuous problems in practice. However, its application on the combinatorial search space is relatively new. The component assignment/sequencing problem in printed circuit board (PCB) has been verified as NP-hard (non-deterministic polynomial time). This paper presents an adaptive particle swarm optimization (APSO) approach to optimize the sequence of component placements on a PCB and the assignment of component types to feeders simultaneously for a pick-and-place machine with multiple heads. The objective of the problem is to minimize the total traveling distance (the traveling time) and the total change time of head nozzle. The APSO proposed in the paper incorporates three heuristics, namely, head assignment algorithm, reel grouping optimization and adaptive particle swarm optimization. Compared with the results obtained by other research, the performance of APSO is not worse than the performance of genetic algorithms (GA) in terms of the distance traveled by the placement head.     

A knowledge-based thermal profile identification advisor for surface mount PCB assembly

Reflow soldering of solder paste is a critical process in the surface mount assembly of printed circuit boards (PCBs). Infrared (IR) radiation and/or forced convection are often used in an oven to heat the PCB assembly and the deposited solder paste to cause the solder to reflow and subsequently form the interconnection between the component terminations and the attachment pads. Control of the reflow soldering process requires the understanding and regulation of several complex variables. Understanding the interrelationships among process control parameters is important in achieving a low defect rate and high yields in reflow soldering. When a variety of components are soldered onto a printed circuit board (PCB) simultaneously in an IR/convection oven through reflow soldering, the process control variables that need to be considered include the characteristics of solder paste used, the size, type, and quantity of components placed on the PCB, the substrate used, the mass and the thermal area of the workpiece, and the conveyor speed.A prerequisite for the achievement of high process yields in the reflow soldering process is the identification of the optimal temperature profile and the range between which the profile is acceptable for the specific assembly. This information is subsequently used by the process engineer to arrive at the relevant temperature of power (wattage) settings for the oven. The in-depth process knowledge required to study the process variables and deduce thermal profiles is not commonly available. Consequently, the objective of this research was to use an expert system approach to help a manufacturing engineer with thermal profile identification in surface mount PCB assembly.The system developed considers the major process control parameters and the interrelationships among them to deduce the optimal temperature profile and a range in which the profile is considered acceptable. The profile identification expert system was developed using PROLOG on a personal computer. Results are displayed using a combination of graphical and textual output. The system was designed to function in a stand-alone capacity. The profile identification expert system's architecture integrates an inference mechanism with the knowledge (facts and rules) provided by the domain expert. It allows the user to update or delete the facts and rules stored in the knowledge base. Consequently, it provides an avenue to enhance the capacity of the system to incorporate domain specific changes.     

Process development for ball grid array assembly using a design of experiments approach

The focus of this work was to develop a robust assembly process for low and high input/output (I/O) ball grid arrays (BGAs). The test vehicles considered had a wide variety of components including full and perimeter array BGAs, and ultrafine pitch peripheral leaded devices. Experimental design techniques were applied in order to identify, screen, and control the parameters that affect the stencil printing process. The factors that affect the process were screened using Tagu-chi-based methodology. These significant factors and their interactions were then further analysed using full factorial designs. The volume and the quality of the solder paste deposits were considered as the response variables. Response surface plots were developed to provide process windows for paste deposition. Process capability studies were performed to evaluate the capability of the solder paste deposition process. Boards were assembled using optimal settings obtained from the experiments. No process-induced defects were found, and 100% yield was obtained.     

废弃电路板插装件的自适应磨削拆解方法

将废弃印制电路板(Printed circuit board,PCB)上的元器件拆解之后再分类,能有效提高后续材料分选和回收的效率。PCB上的插装式元器件由于引脚弯曲等原因,所需拆解力很大,常用的方法难以做到有效拆解。为解决这一困难,提出自适应磨削拆解方法,利用弹簧的自适应调节能力,在处理挠曲不平的PCB时提供较为平稳的法向磨削力。对自适应磨削系统的力学特性进行分析,结论显示在采用合理的磨削参数时,能够快速去除引脚并且不会过多地降低基板的刚度,证明了自适应磨削拆解方法的可行性。基于此自适应磨削系统的原理研制废弃PCB插装式元器件的引脚磨削拆解原型设备,并进行验证试验研究。试验结果表明此方法能够在轻微磨削基板的条件下高效地去除引脚,磨削后元器件的自动脱落率达到90%以上,并且未脱落的元器件与基板的连接强度大幅降低。     

Expert system based placement sequence identification for surface mount PCB assembly

Component placement is a critical and time consuming task in the assembly of surface mount printed circuit boards (PCBs). The past decade has witnessed the need for high speed, accurate, and repeatable placement procedures in the PCB assembly domain. At the same time, manufacturing engineers are faced with demands to reduce flow-time and increase throughput rates in order to increase productivity. A consequence of these trends has been the need to identify acceptable (possibly optimal) placement sequences during surface mount PCB assembly.The focus of this research was the identification of near optimal solutions for the placement sequence identification problem while considering machine and process constraints in a manufacturing environment. Expert (or knowledge-based) systems were used as the solution method for this problem. PROLOG, a popular language for artificial intelligence applications, was used in this research. The prototype knowledge-based system developed in this research identifies solutions in (almost) real-time.     

SMT-TAB: A process planning system for PCB assembly using TAB and SMT

Process planning is a critical function in any manufacturing domain. This is especially true in the electronics manufacturing area where substantial heuristic and experiential knowledge is commonly used during process plan development. While research in computer-aided process planning (CAPP) has tended to concentrate in the machining realm, few CAPP systems have been developed for electronics manufacturing applications and more specifically for the printed circuit board (PCB) assembly domain. Besides, the CAPP systems that have been developed for this area have dealt with either insertion mount or surface mount PCB assembly processes only.Tape automated bonding (TAB), though a relatively new technology, is gaining importance in electronics assembly owing to its inherent advantages. The advent of fine pitch technology together with the ever increasing need for more inputs/outputs and greater pin counts in integrated circuit applications has enhanced the use of TAB technology in electronics manufacturing. This trend has been further augmented by the increasing need for compactness in consumer electronics.This research designed and developed a prototype CAPP system for the PCB assembly domain. The system developed generates a process plan for PCBs populated with surface mount and/or TAB components. An artificial-intelligence based expert system approach has been used in the design and development of the CAPP system. Outputs generated by the system are presented along with ideas for future research.     

电子元件焊接质量的自动光学检测系统研究

为满足表面贴装电子元件的高密度化、小型化、零缺陷等要求,设计一种电子元件焊接质量的自动光学检测系统,可将缺件、多锡、少锡、假焊等焊接缺陷检查出来。该系统首先通过图像采集系统获取电路板图像,并提取元件的检测窗口,通过图像处理得到相应的图像特征,对其特征进行尺寸的测量和识别,然后与标准数据进行比较,判断元件表面焊接质量是否合格,以达到检测元件的目的。系统具有运行平稳、操作方便、智能化和模块化等特点,满足实际生产的需要。     

表面组装技术生产线贴片机负荷均衡优化

典型的表面组装技术生产线是由高速机和多功能机串联而成,印制电路板卜的元器件在贴片机之间的负荷均衡优化问题是表面组装技术生产调度的关键问题.以使贴片时间与更换吸嘴时间之和最大的工作台生产时间最小化为目标,构建了负荷均衡模型,开发了相应的遗传算法,并进行了数值实验与算法评价.与生产时间理论下界和现场机器自带软件调度方案的对比,验证了模型及其算法的有效性.     

Internet-based electronics manufacturing troubleshooting tool for surface mount PCB assembly

Increasing product complexity, decreasing component size, and using double-sided boards have made surface mount technology (SMT) based electronics manufacturing (EM) components more difficult to assemble. This has resulted in the economic troubleshooting of EM defects being one of the main problems facing all manufacturers. Although the authors have made significant improvements in the EM process, it has been shown that the implemented changes in the automated lines have not yet produced a high enough percentage of reliable finished products. The objective of this current development is to make a contribution towards these EM processes by creating an Internet-based intelligent system of circuit board defect detection so that EM process flaws that necessitate rework operations can be identified prior to manufacturing runs. With the development of this system, the need to rework the defective components will be minimized for any assembly line and assembly line process parameters, which cause some reliability problems (such as solder balls, insufficient solder at joints, burnt joint connections, bridged leads, voids, skewed leads, and unformed joints) will be troubleshot directly, and the rework will be greatly reduced from the EM assembly line. This paper reports the current development and its structure.     

Optimization of PCB component placements for the collect-and-place machines

This paper presents two hybrid genetic algorithms (HGAs) to optimize the component placement operation for the collect-and-place machines in printed circuit board (PCB) assembly. The component placement problem is to optimize (i) the assignment of components to a movable revolver head or assembly tour, (ii) the sequence of component placements on a stationary PCB in each tour, and (iii) the arrangement of component types to stationary feeders simultaneously. The objective of the problem is to minimize the total traveling time spent by the revolver head for assembling all components on the PCB. The major difference between the HGAs is that the initial solutions are generated randomly in HGA1. The Clarke and Wright saving method, the nearest neighbor heuristic, and the neighborhood frequency heuristic are incorporated into HGA2 for the initialization procedure. A computational study is carried out to compare the algorithms with different population sizes. It is proved that the performance of HGA2 is superior to HGA1 in terms of the total assembly time.     

RELIABILITY OF TEST LANDS TARGETING IN BED-OF-NAILS STYLE TEST FIXTURE

A systematic, accurate and robust evaluating method for fine pitch printed circuit board (PCB) positioning assessment in testing fixture is developed. Targeting reliability of bed-of-nails tester is successfully evaluated by the 2D pattern transform. Probe offset vector with its Weibull and Gaussian distribution estimates are obtained for further investigation about the causes of misalignment on the basis of a batch tests for same kind of PCBs.     

印制电路板组装工艺规划与调度集成建模及优化方法

针对印制电路板(Printed circuit board,PCB)组装工艺与调度集成优化问题,建立集成的优化数学模型,提出将多色集合(Polychromatic set,PS)与遗传算法(Genetic algorithm,GA)相结合的新的优化方法。利用多色集合的逻辑围道矩阵和数值围道矩阵建立集成优化问题的约束模型。将约束模型与GA的遗传编码、遗传操作和适应度值计算等结合,保证GA始终在有效的解空间中进行搜索。不仅能提高遗传搜索的效率,还可以通过约束模型的修改,动态描述设备故障和PCB组装任务变化等不确定因素的影响,使得算法具有良好的适应性。实例计算结果表明,该方法能高效地实现PCB组装工艺规划与调度的集成优化,缩短PCB组装完工时间,减少交货期延迟,平衡设备的工作负荷。     

A concurrent development tool for flexible assembly systems

Global competition and the rapid pace of technological change now require the almost continual introduction of product upgrades by any manufacturer. Thus, such a manufacturer is likely to market older and newer versions of a product simultaneously, not to mention niche-specific editions of any product upgrade. An increasingly successful response to this product proliferation is the implementation of flexible assembly systems. In the context of a flexible assembly system (FAS), the ability to estimate the impact of various product and process options on the maximal level of system output becomes crucial to managing the ever-changing product mix. This paper presents a tool for such impact estimation that can facilitate concurrent development and engineering. Experience with an actual FAS is the basis for the reported results. The tool is a specialized combination of discreteevent computer simulation, experimental design, and regression analysis. Application of the tool assumes FAS use with a cellular manufacturing philosophy. Thus, uncluttered process flow for a family of products in the sense of group technology places the focus on potential bottlenecks. The new tool here models the impact of process and product options on bottleneck and, hence, FAS behavior.Working paper presented at the Third ORSA/TIMS Special Interest Conference on Flexible Manufacturing Systems, August 14–16, 1989, M.I.T., Cambridge, Massachusetts.     

Optimisation of the Substrate Preheat Temperature for the Encapsulation of Flip Chip Devices

This research addressed the feasibility of using a substrate preheat temperature which is higher than the manufacturer’s recommendation in order to reduce the cycle time of the encapsulation process while still ensuring package reliability. temperature are discussed and evaluated. A statistical model was generated to help determine the optimal substrate preheat temperature for given chip dimensions, standoff height, surface texture, etc. Using the substrate preheat temperature determined by the model, the flow time of the encapsulant could be reduced by more than a factor of two while still ensuring a 6s quality level.     

A study of microvias produced by laser-assisted seeding mechanism in blind via hole plating of printed circuit board

The laser-assisted seeding (LAS) mechanism has the potential to replace the conventional electroless copper plating in printed circuit board (PCB) manufacture because it combines the steps of drilling and electroless plating into one. The LAS mechanism should be able to plate microvias with high aspect ratio that may not be feasible by conventional electroless plating due to the small via geometry. The conventional electroless plating process generates considerable quantities of chemical waste. In particular, the plating of microvia with high aspect ratio close to 1 is difficult due to the limited accessibility of chemical solution to the via internal wall surface in conventional plating technology. LAS is a promising alternative. The objectives of this paper are to report the deposition mechanism of a thin copper film layer (laser-assisted seeding) on PCB microvias dielectric and to study the thermal reliability of the microvias produced by this mechanism. Results find that the microvias produced by LAS are thermally and electrically as reliable as conventional electroless plating technology. This revised version was published online in October 2004 with a correction to the issue number.     

电感式角度传感器电磁耦合敏感元件的研究

针对传统角度传感器结构复杂、制造成本高,且不易于嵌入式安装等不足,设计研究了一种基于PCB板的平面电感式角度传感器上的电磁耦合敏感元件。分析了此电感式角度传感器的实现机理,根据实现机理,建立了理论模型;在ANSYS Maxwell软件中创建了激励线圈、接收线圈和转子的实体模型,并进行了电磁耦合仿真分析,仿真结果验证了设计的合理性与可行性。根据理论模型制作原型敏感元件,在角度传感器实验台上进行电磁耦合实验,得到转子转动角度与接收信号峰峰值变化的对应关系,分析其影响因素。改进设计,对改进型敏感元件进行电磁耦合实验,实验结果表明改进型敏感元件提高了角度检测的灵敏度,3组接收信号峰峰值变化曲线中间部分线性度良好,且能完整覆盖一个变化周期。     

Activity-based cost-modelling procedures for PCB assembly

Accurate product cost estimation is important in decisions which involved the selection of the least-cost design among alternative designs and the economic feasibility of a product. An accurate cost-estimating procedure would include the cost of materials and all activities that incur cost.This paper presents the development of cost models for printed circuit board (PCB) assembly which will take into consideration activities that incur cost owing to complexity, volume and batch size of PCB manufactured. All activities are allocated into three level bases and they are unit-level cost, batch-level cost and product-level cost. The cost of assembling one PCB is the summation of all these three costs. A case example is presented to illustrate the application of the models developed.     

某直升机机载设备印制板振动试验失效分析

文中以某机载电子设备振动试验中印制板（PCB）故障现象为研究对象,通过理论分析和ANSYS动力学计算的方法对PCB板产生故障的机理进行了分析和计算。计算结果与试验现象相符,认为谐振和PCB板设计问题是导致该试验故障的原因,并在结构接口方面对引起谐振的情况进行了分析,阐述了结构和电讯方面相应的改进措施。     

An Inexpensive Sequential Injection Analyzer for the Analytical Laboratory

Abstract

A home‐made multiposition valve and a syringe pump were specially designed and fabricated using inexpensive and easily available materials and equipment in the laboratory. The hardware and software for controlling the devices and displaying the signal were developed. Both devices were combined to obtain a sequential injection analysis (SIA) system and used by incorporating with a spectrophotometric detector. The developed SIA analyzer is computerized. The SIA system can select the samples and reagent, which is then sequentially injected into the holding coil where the sample and the reagent zones are taking place. Both sample and reagent zones are delivered into a flow‐through detector where the reaction product is measured spectrophotometrically. The program for interfacing the SIA instrumentation with a personal computer was also developed using Microsoft Visual Basic?. This can enable a wide range of chromophores to be automatically detected. The fabricated SIA analyzer was tested for determining Fe(III) in standard solution based on Fe(III)‐thiocyanate complex. The RSD for 11 replicates determination of 4.0 mg/L iron was 1.08%. The detection limit (3σ) and the determination limit (10σ) were 0.34 and 1.13 mg/L, respectively. A linear calibration curve over the range of 1.0–7.0 mg/L iron and correlation coefficient of 0.9977 were established. The analyzer has been successfully applied to the determination of total iron in waters. Results obtained by both the proposed SIA and AAS methods were in excellent agreement.