高K栅堆叠结构MOSFET器件阈值电压不稳定度的半经验解析模型

A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration.     

Compact analytical model for single gate AlInSb/InSb high electron mobility transistors

We have developed a 2D analytical model for the single gate Al In Sb/In Sb HEMT device by solving the Poisson equation using the parabolic approximation method.The developed model analyses the device performance by calculating the parameters such as surface potential,electric field distribution and drain current.The high mobility of the Al In Sb/In Sb quantum makes this HEMT ideal for high frequency,high power applications.The working of the single gate Al In Sb/In Sb HEMT device is studied by considering the variation of gate source voltage,drain source voltage,and channel length under the gate region and temperature.The carrier transport efficiency is improved by uniform electric field along the channel and the peak values near the source and drain regions.The results from the analytical model are compared with that of numerical simulations(TCAD) and a good agreement between them is achieved.     

A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

In analog circuit design an important parameter,from the perspective of superior device performance,is linearity.The DG MOSFET in asymmetric mode operation has been found to present a better linearity.In addition to that it provides,at the discretion of analog circuit designer,an additional degree of freedom,by providing independent bias control for the front and the back gates.Here a non-quasi-static(NQS)small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD simulations.The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance,Cgd1and Cgd2,the intrinsic front and back distributed channel resistance,Rgd1and Rgd2respectively,the transport delay,m,and the inductance,Lsd.The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data,for symmetric DG MOSFET devices,from the available literature.The device simulation is performed with respect to frequency up to 100 GHz.     

多栅指AlGaN/GaN HEMT器件自热效应研究

Self-heating in multi-finger AlGaN/GaN high-electron-mobility transistors(HEMTs) is investigated by measurements and modeling of device junction temperature under steady-state operation.Measurements are carried out using micro-Raman scattering to obtain the detailed and accurate temperature distribution of the device.The device peak temperature corresponds to the high field region at the drain side of gate edge.The channel temperature of the device is modeled using a combined electro-thermal model considering 2DEG transport characteristics and the Joule heating power distribution.The results reveal excellent correlation to the micro-Raman measurements, validating our model for the design of better cooled structures.Furthermore,the influence of layout design on the channel temperature of multi-finger AlGaN/GaN HEMTs is studied using the proposed electro-thermal model, allowing for device optimization.     

Compact Threshold Voltage Model for FinFETs

A 2D analytical electrostatics analysis for the cross-section of a FinFET (or tri-gate MOSFET) is performed to calculate the threshold voltage.The analysis results in a modified gate capacitance with a coefficient Ｈ introduced to model the effect of trigates and its asymptotic behavior in 2D is that for double-gate MOSFET.The potential profile obtained analytically at the cross-section agrees well with numerical simulations.A compact threshold voltage model for FinFET,comprising quantum mechanical effects,is then proposed.It is concluded that both gate capacitance and threshold voltage will increase with a decreased height,or a decreased gate-oxide thickness of the top gate，which is a trend in FinFET design.     

Modeling and simulation of centroid and inversion charge density in cylindrical surrounding gate MOSFETs including quantum effects

An analytical model for surrounding gate metal–oxide–semiconductor field effect transistors(MOSFETs)considering quantum effects is presented.To achieve this goal,we have used a variational approach for solving the Poisson and Schrodinger equations.This model is developed to provide an analytical expression for the inversionchargedistributionfunctionforallregionsofthedeviceoperation.Thisexpressionisusedtocalculatethe other important parameters like the inversion charge centroid,threshold voltage and inversion charge density.The calculated expressions for the above parameters are simple and accurate.The validity of this model was checked for the devices with different device dimensions and bias voltages.The calculated results are compared with the simulation results and they show good agreement.     

An optimized junctionless GAA MOSFET design based on multi-objective computation for high-performance ultra-low power devices

An analytical investigation has been proposed to study the subthreshold behavior ofjunctionless gates all around （JLGAA） MOSFET for nanoscale CMOS analog applications. Based on 2-D analytical analysis, a new subthreshold swing model for short-channel JLGAA MOSFETs is developed. The analysis has been used to calculate the subthreshold swing and to compare the performance of the investigated design and conventional GAA MOSFET, where the comparison of device architectures shows that the JLGAA MOSFET exhibits a superior performance with respect to the conventional inversion-mode GAA MOSFET in terms of the fabrication process and electrical behavior in the subthreshold domain. The analytical models have been validated by 2-D numerical simulations. The proposed analytical models are used to formulate the objectives functions. The overall objective function is formulated by means of a weighted sum approach to search the optimal electrical and dimensional device parameters in order to obtain the better scaling capability and the electrical performance of the device for ultra-low power applications.     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET''''s

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region, for it can suppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energy transport model, using two-dimensional device simulator Medici, the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studied and compared with that of counterpart conventional planar device in this paper. The examined structure parameters include negative junction depth, concave corner and effective channel length. Simulation results show that grooved gate device can suppress hot carrier effect deeply even in deep sub-micron region. The studies also indicate that hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device. With the increase of concave corner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the redu     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET’s

Grooved gate structure Metal-Oxide-Semiconductor(MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region,for it can suppress hot carrier effect and short channel effect deeply.Based on the hydrodynamic energy transoprt model,using two-dimensional device simulator Medici,the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel Mosfet‘s is studied and compared with that of counterpart conventional planar device in this paper.The examined structure parameters include negative junction depth,conventinal planar device in this paper.The examined structure parameters include negative junction depth,concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device.With the increase of concave corner,the hot carrier effect in groovd gate MOSFET decreases sharply,and with the reducing of effective channel length,the hot carrier effect becomes large.     

Flicker and thermal noise in an n-channel underlap DG FinFET in a weak inversion region

We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method,i.e.,the virtual source.The flicker and thermal noise spectral density models are also developed using these charge and current models expression.The model is validated with already published experimental results of flicker noise for DG FinFETs.For an ultrathin body,the degradation of effective mobility and variation of the scattering parameter are considered.The effect of device parameters like gate length L_g and underlap length L_un on both flicker and thermal noise spectral densities are also analyzed.Increasing L_g and L_un,increases the effective gate length,which reduces drain current,resulting in decreased flicker and thermal noise density.A decrease of flicker noise is observed for an increase of frequency, which indicates that the device can be used for wide range of frequency applications.     

Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency

We propose a new two-dimensional (2-D) analytical model of a dual material gate MOSFET (DMG-MOSFET) for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one. The arrangement is such that the work function of the gate metal near the source is higher than the one near the drain. The model so developed predicts a step-function in the potential along the channel, which ensures screening of the drain potential variation by the gate near the drain. The small difference of voltage due to different gate material keeps a uniform electric field along the channel, which in turn improves the carrier transport efficiency. The ratio of two metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. The model is verified by comparison to the simulated results using a 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions

Physics-based analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions is presented. The effect of inversion carriers on the channel’s potential is considered in presented model. Using this analytical model, the characteristics of EJ-CSG are investigated in terms of surface potential and electric field distribution, threshold voltage roll-off, and DIBL. Results show that the application of electrically induced S/D extensions to the cylindrical surrounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, and DIBL. It is also revealed that a moderate side-gate bias voltage, a small gate oxide thickness, and a small silicon channel radius are needed to improve device characteristics. The derived analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.     

Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs-InGaAs symmetric double-gate HEMT

This paper presents an approximate solution of a 2-D Poisson’s equation in the channel region, based on physical correspondence between MOSFET and HEMT, with the approximation that the vertical channel potential distribution is a cubic function of position to study not only tied gate but separate gate bias conditions as well. An analytical expression for both front and back heterointerface potential is derived and threshold voltage is obtained iteratively from the proposed potential model. The threshold voltage behavior for tied and separated double-gate HEMT is investigated for various device dimensions. The back gate effect of the separated double gate HEMT is investigated for the depleted back channel only. The results obtained are verified by comparing them with simulated and experimental results.     

Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects

Two-dimensional (2-D) analytical modeling for a novel multiple region MOSFET device architecture-Tri-Material Gate Stack MOSFET-is presented, which shows reduced short-channel effects at short gate lengths. Using a three-region analysis in the horizontal direction and a universal depletion width boundary condition, the 2-D potential and electric field distribution in the channel region along with the threshold voltage of the device are obtained. The proposed model is capable of modeling electrical characteristics like surface potential, electric field, and threshold voltage of various other existent MOSFET structures like dual-material-gate, electrically induced shallow junction/straddle-gate (side-gate), and single-material-gate MOSFETs, with and without the gate stack architecture. The 2-D device simulator ATLAS is used over a wide range of parameters and bias conditions to validate the analytical results.     

Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs

This article presents an analytical surface potential, threshold voltage and drain current model for asymmetric pocket-implanted, single-halo dual material gate and double-halo dual material gate (DHDMG) n-MOSFET (MOSFET, metal–oxide–semiconductor field-effect transistor) operating up to 40?nm regime. The model is derived by applying Gauss's law to a rectangular box, covering the entire depletion region. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends along with the inner fringing capacitances at both the source and the drain ends and the subthreshold drain and the substrate bias effect. Using the surface potential model, the threshold voltage and drain currents are estimated. The same model is used to find the characteristic parameters for dual-material gate (DMG) with halo implantations and double gate. The characteristic improvement is investigated. It is concluded that the DHDMG device structure exhibits better suppression of the short-channel effect (SCE) and the threshold voltage roll-off than DMG and double-gate MOSFET. The adequacy of the model is verified by comparing with two-dimensional device simulator DESSIS. A very good agreement of our model with DESSIS is obtained proving the validity of our model used in suppressing the SCEs.     

A 2D Transconductance and Sub-threshold behavior model for triple material surrounding gate (TMSG) MOSFETs

A 2D analytical model for transconductance, Sub-threshold current and Sub-threshold swing for Triple Material Surrounding Gate MOSFET (TMSG) is presented in this paper. Based on the solution of two dimensional Poisson equation, the physics based model of sub-threshold current of the device is derived. The model also includes the effect of gate oxide thickness and silicon thickness on the sub-threshold swing characteristics. Transconductance to drain current ratio of the triple material surrounding gate is calculated since it is a better criterion to access the performance of the device. The effectiveness of TMSG design was scrutinized by comparing with other triple material and dual material gate structures. Moreover the effect of technology parameter variations is also studied and proposed. This proposed model offers basic guidance for design of TMSG MOSFETs. The results of the analytical model are compared with the MEDICI simulation results thus providing validity of the proposed model.     

Monte Carlo surface scattering simulation in MOSFET structures

The Monte Carlo method has been applied to MOSFET devices with the gate lengths less than 1 µm. The electric field in the channel was obtained by an analytical approach. Since the classical situation is approached in the submicrometer gate device, the partial diffusive model is employed for surface scattering process. Transient phenomena such as velocity overshoot have been predicted with drain biases causing a large field gradient in the channel. Comparison of the results of the Monte Carlo simulation with those obtained by an analytical approach based on static mobility shows that the carrier transit time in the channel is shorter (as much as two times) than that predicted by the analytical approach for a 0.3 µm gate device.