Testability of 2-Level AND/EXOR Circuits

It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement, however, only holds true for circuits derived from restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller and fixed polarity Reed-Muller expressions. For these two classes of expressions, circuits with good deterministic testability properties are known. In this paper we show that these circuits also have good random pattern testability attributes. An input probability distribution is given that yields a short expected test length for biased random patterns. This is the first time theoretical results on random pattern testability are presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. It turns out that analogous results cannot be expected for less restricted classes of 2-level AND/EXOR circuits. We present experiments demonstrating that generally minimized 2-level AND/OR circuits can be tested as easy (or hard) as minimized 2-level AND/EXOR circuits.     

Wavelet packet transform initialization for piecewise polynomialand bandlimited inputs

This paper considers the problem of initializing the wavelet packet transform when the analog input x(t) is either bandlimited or else is piecewise polynomial on the dyadic intervals. This is accomplished by the construction of certain prefilter sequences that are applied to the samples {x_k|x_k=x(kT)} (T is the sampling period). In the piecewise polynomial case, the prefilter sequences are computed with the aid of the interpolatory graphical display algorithm (IGDA), which is used to compute the so-called incremental moment functions of the scaling function φ(t) on the dyadic points. The moments of φ(t) are also employed     

An efficient approach to ARMA modeling of biological systems withmultiple inputs and delays

Presents a new approach to AutoRegressive Moving Average (ARMA or ARX) modeling which automatically seeks the best model order to represent investigated linear, time invariant systems using their input/output data. The algorithm seeks the ARMA parameterization,which accounts for variability in the output of the system due to input activity and contains the fewest number of parameters required to do so. The unique characteristics of the proposed system identification algorithm are its simplicity and efficiency in handling systems with delays and multiple inputs. The authors present results of applying the algorithm to simulated data and experimental biological data. In addition, a technique for assessing the error associated with the impulse responses calculated from estimated ARMA parameterizations is presented. The mapping from ARMA coefficients to impulse response estimates is nonlinear, which complicates any effort to construct confidence bounds for the obtained impulse responses. Here a method for obtaining a linearization of this mapping is derived, which leads to a simple procedure to approximate the confidence bounds     

高效剩余数至二进制转换器设计

针对目前剩余数系统所处理数据动态范围较小。而且剩余数至二进制转换器的面积和延迟较大等方面的问题,基于新中国余数定理II提出了一个高效并行转换算法,同时给出相应的电路实现。该算法采用模集合（2^n-1,2^n＋1,2^2n,2^2n＋1,可同时处理4个模,处理数的动态范围达到6n＋l位。乘法逆元简单,电路完全由基本的加法器构成,硬件实现容易。分析实验结果表明,相比同类模集合反向转换器,文中提出的转换器的面积节省了39．4％,速度提高了47．4％。     

Modular design of soft-switching circuits for two-level and three-level inverters

This paper presents a negative-bus auxiliary resonant circuit (NBARC) and novel mirror symmetrical pair of resonant link modules for soft commutation of two-level and three-level inverters. The NBARC topology reduces the power device counts and requires low device power ratings. While the basic NBARC resonant circuit is conceived and analyzed for zero-voltage switching (ZVS) of two-level inverters, the topology and modular design approach are extended to form a pinched-link resonant stage of ZVS for three-level inverters using mirror-symmetrical pair of resonant modules. The circuit is also designed as an optional module that can be attached to a standard inverter bridge and converted into a soft-switched inverter. Experimental results verify our circuit analysis and implementation.     

A MAC/PHY cross-layer design for efficient ARQ protocols

In many wireless data systems, automatic repeat request (ARQ) and hybrid automatic repeat request (HARQ) work independently. In this paper, we introduce a new ARQ feedback scheme called Cross-Layer ARQ (CL-ARQ), where ARQ closely interoperates with HARQ by making use of the acknowledgement of HARQ internally. By doing so, CL-ARQ not only removes the overhead for ARQ acknowledgement messages, but also improves the average delivery delay and TCP throughput. Especially, when the entities in charge of HARQ and ARQ are located far apart geographically, CL-ARQ remarkably outperforms the legacy scheme.     

An efficient Fourier transform algorithm for multitone harmonicbalance

A novel Fourier transform technique is proposed for use in multitone harmonic-balance (HB) simulations. It is shown that computations of multitone distorted spectra reduce to efficient one-dimensional fast Fourier transform operations when certain relationships exist between the sampling rate and frequency components of the signal. The algorithm requires minimal initialization time and is readily incorporated into existing HE tools. It is especially useful when the number of input tones is very large, such as spectral regrowth and noise-power ratio simulations. The method is demonstrated on the example of a 5-GHz MESFET amplifier driven by a quadrature phase shift-keying modulated carrier     

Hardware efficient fast computation of the discrete fourier transform

Typographical errors were printed in the print and online versions of the original article. The correct versions of Equation 25 (page 168), Figure 6(c) (page 169), and Table 2 (page 170) are printed below, respectively. The online version of the original article can be found at     

二维离散5/3小波变换并行VLSI结构设计

提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。     

Energy efficient network design tool for green IP/Ethernet networks

An innovative energy-efficient network design algorithm and a tool to lower the network power consumption are proposed. The goal is an energy efficient network that carries its rated communication load while meeting the QoS requirements by using the minimum set of nodes and links. QoS metrics include hop limit, bandwidth limit reliability and stability. The proposed algorithm addresses the set-covered problem. To discover the optimum network configuration efficiently, we propose a network configuration generation algorithm that utilizes DAPDNA-2, a parallel data flow type reconfigurable processer. The processor automatically produces the node/link set in n-digit binary form where links are modeled as “1” for power on and “0” for power off; it also confirms that the QoS requirements are satisfied. Evaluation results show that DAPDNA-2 is 2-orders faster than the conventional sequential method running on a Pentium-4 processor. Prototype Gigabit Layer-2 switches having remote link power on/off and traffic monitoring functions are developed. Using these switches, we successfully demonstrate an energy efficient IP/Ethernet network. The evaluation results show that network power savings of up to 30% can be realized under the NFSNET topology model. The proposed algorithm and power efficient network architecture can be applied to realize the future green network.     

A mixed transform approach for efficient compression of medical images

A novel technique is presented to compress medical data employing two or more mutually nonorthogonal transforms. Both lossy and lossless compression implementations are considered. The signal is first resolved into subsignals such that each subsignal is compactly represented in a particular transform domain. An efficient lossy representation of the signal is achieved by superimposing the dominant coefficients corresponding to each subsignal. The residual error, which is the difference between the original signal and the reconstructed signal is properly formulated. Adaptive algorithms in conjunction with an optimization strategy are developed to minimize this error. Both two-dimensional (2-D) and three-dimensional (3-D) approaches for the technique are developed. It is shown that for a given number of retained coefficients, the discrete cosine transform (DCT)-Walsh mixed transform representation yields a more compact representation than using DCT or Walsh alone. This lossy technique is further extended for the lossless case. The coefficients are quantized and the signal is reconstructed. The resulting reconstructed signal samples are rounded to the nearest integer and the modified residual error is computed. This error is transmitted employing a lossless technique such as the Huffman coding. It is shown that for a given number of retained coefficients, the mixed transforms again produces the smaller rms-modified residual error. The first-order entropy of the error is also smaller for the mixed-transforms technique than for the DCT, thus resulting in smaller length Huffman codes.     

Peak transform for efficient image representation and coding.

In this work, we introduce a nonlinear geometric transform, called peak transform (PT), for efficient image representation and coding. The proposed PT is able to convert high-frequency signals into low-frequency ones, making them much easier to be compressed. Coupled with wavelet transform and subband decomposition, the PT is able to significantly reduce signal energy in high-frequency subbands and achieve a significant transform coding gain. This has important applications in efficient data representation and compression. To maximize the transform coding gain, we develop a dynamic programming solution for optimum PT design. Based on PT, we design an image encoder, called the PT encoder, for efficient image compression. Our extensive experimental results demonstrate that, in wavelet-based subband decomposition, the signal energy in high-frequency subbands can be reduced by up to 60% if a PT is applied. The PT image encoder outperforms state-of-the-art JPEG2000 and H.264 (INTRA) encoders by up to 2-3 dB in peak signal-to-noise ratio (PSNR), especially for images with a significant amount of high-frequency components. Our experimental results also show that the proposed PT is able to efficiently capture and preserve high-frequency image features (e.g., edges) and yields significantly improved visual quality. We believe that the concept explored in this work, designing a nonlinear transform to convert hard-to-compress signals into easy ones, is very useful. We hope this work would motivate more research work along this direction.     

Modified butterfly structure for efficient implementation of prunedfast cosine transform

In the computation of pruned fast cosine transforms (FCTs), overheads are unavoidable in order to keep track of the complete and incomplete butterflies in each stage. The authors present a modification to the FCT butterfly structure proposed to reduce these overheads. Using this modified structure, the computation of the coefficients can be stopped at any point and resumed from the same point without any overhead. This structure also performs well for complete computation of FCTs     

An efficient algorithm to solve integer-programming problemsarising in system-reliability design

A simple and efficient technique for solving integer-programming problems that normally arise in system-reliability design is introduced. It quickly solves even a very large system problem. It consists of a systematic search near the boundary of constraints and involves functional evaluations only. It can handle system-reliability design problems of any type in which the decision variables are restricted to integer values. Several illustrative examples are given to substantiate these assertions     

二维9／7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9／7小波变换（DWT）Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点。这种并行处理的Mesh结构可提高小渡变换电路速度,以及图像压缩的速度。     

二维9/7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9/7小波变换(DWT)Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点.这种并行处理的Mesh结构可提高小波变换电路速度,以及图像压缩的速度.     

Direction-adaptive fixed length discrete cosine transform framework for efficient H.264/AVC video coding

The 2D-discrete cosine transform (2D-DCT) is one of the popular transformation for video coding. Yet, 2D-DCT may not be able to efficiently represent video data with fewer coefficients for oblique featured blocks. To further improve the compression gain for such oblique featured video data, this paper presents a directional transform framework based on direction-adaptive fixed length discrete cosine transform (DAFL-DCT) for intra-, and inter-frame. The proposed framework selects the best suitable transform mode from eight proposed directional transform modes for each block, and modified zigzag scanning pattern rearranges these transformed coefficients into a 1D-array, suitable for entropy encoding. The proposed scheme is analysed on JM 18.6 of H.264/AVC platform. Performance comparisons have been made with respect to rate-distortion (RD), Bjontegaard metrics, encoding time etc. The proposed transform scheme outperforms the conventional 2D-DCT and other state-of-art techniques in terms of compression gain and subjective quality.     

CAD tools for efficient RF/microwave transistor modeling and circuit design

In today’s radiofrequency and microwave communication circuits, there is an ever-increasing demand for higher integration and miniaturization. This trend leads to massive computational tasks during simulation, optimization and statistical analyses, requiring robust modeling tools so that the whole process can be achieved reliably. In this paper, the authors proposed frequency- and time-domain computer-aided design tools that can characterize RF/microwave field effect and heterojunction bipolar transistors and efficiently predict a circuit performance. The proposed tools are demonstrated through examples.     

Computationally efficient systolic architecture for computing the discrete Fourier transform

A new high-performance systolic architecture for calculating the discrete Fourier transform (DFT) is described which is based on two levels of transform factorization. One level uses an index remapping that converts the direct transform into structured sets of arithmetically simple four-point transforms. Another level adds a row/column decomposition of the DFT. The architecture supports transform lengths that are not powers of two or based on products of coprime numbers. Compared to previous systolic implementations, the architecture is computationally more efficient and uses less hardware. It provides low latency as well as high throughput, and can do both one- and two-dimensional DFTs. An automated computer-aided design tool was used to find latency and throughput optimal designs that matched the target field programmable gate array structure and functionality.