共查询到20条相似文献,搜索用时 31 毫秒
1.
Polishchuk I. Yee-Chia Yeo Qiang Lu Tsu-Jae King Chenming Hu 《Device and Materials Reliability, IEEE Transactions on》2001,1(3):158-162
The degradation of 100-nm effective channel length pMOS transistors with 14 Å equivalent oxide thickness Jet Vapor Deposition (JVD) Si3N4 gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concern. Hot-carrier reliability of 14 Å Si3N4 transistors is compared to reliability of 16 Å SiO2 transistors 相似文献
2.
ManjulaRani K.N. Rao V.R. Vasi J. 《Device and Materials Reliability, IEEE Transactions on》2004,4(1):18-23
In this paper, we study the stress voltage polarity-dependent reliability of n-channel metal-nitride-silicon field-effect transistors (MNSFETs) with ultrathin jet vapor deposited (JVD) silicon nitride dielectric. Under constant voltage stress, device parameters such as threshold voltage and transconductance degrade. Charge trapping due to interface and bulk traps is observed. Our study shows that the degradation is polarity dependent. MNSFETs show lower degradation under positive stress fields. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform MOSFETs, but under negative stressing, MNSFETs show more degradation. 相似文献
3.
Byoung Hun Lee Rino Choi Sim J.H. Krishnan S.A. Peterson J.J. Brown G.A. Bersuker G. 《Device and Materials Reliability, IEEE Transactions on》2005,5(1):20-25
Charge trapping in high-/spl kappa/ gate dielectrics affects the result of electrical characterization significantly. DC mobility degradation and device threshold voltage instability and C-V and I-V hysteresis are a few examples. The charging effects in high-/spl kappa/ gate dielectric also affect the validity of conventional reliability test methodologies developed for SiO/sub 2/ devices. In this paper, we review high-/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl kappa/ devices. 相似文献
4.
Salman A. Gauthier R. Stadler W. Esmark K. Muhammad M. Putnam C. Ioannou D.E. 《Device and Materials Reliability, IEEE Transactions on》2002,2(1):2-8
In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/Lnpn protection devices in a 0.13-μm CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 μm) devices fail because of source/drain filamentation, whereas longer (0.3 μm) devices with thin (22 Å) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on It2. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device 相似文献
5.
Sim J.H. Byoung Hun Lee Rino Choi Seung-Chul Song Bersuker G. 《Device and Materials Reliability, IEEE Transactions on》2005,5(2):177-182
Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-/spl kappa/ gate stack devices are severe than the one in the SiO/sub 2//poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress. 相似文献
6.
Watling J.R. Lianfeng Yang Asenov A. Barker J.R. Roy S. 《Device and Materials Reliability, IEEE Transactions on》2005,5(1):103-108
Scaling of Si MOSFETs beyond the 90-nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilizing strained Si (SSi) channels. Additionally, high-/spl kappa/ dielectrics are expected to replace SiO/sub 2/ around or after the 45-nm node to reduce the gate leakage current problem, facilitating further scaling. However, aside from the many technological issues such as trapped charge and partial crystallization of the dielectric, both of which are major issues limiting the reliability and device performance of devices employing high-/spl kappa/ gate stacks, a fundamental drawback of MOSFETs with high-/spl kappa/ dielectrics is the mobility degradation due to strong soft optical phonon scattering. In this work we study the impact of soft optical phonon scattering on the mobility and device performance of conventional and strained Si n-MOSFETs with high-/spl kappa/ dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 25-nm. Additionally we have also briefly investigated the effect (the percentage change) that a trapped charge within the gate oxide will have on the drive current for both a SiO/sub 2/ oxide and an equivalent oxide thickness of high-/spl kappa/ dielectric. 相似文献
7.
Fukai Y.K. Sugitani S. Enoki T. Yamane Y. 《Device and Materials Reliability, IEEE Transactions on》2008,8(2):289-296
We examined the issue of reliability of InP-based high-electron mobility transistors (HEMTs), focusing on the increase of drain resistance Rd. In investigations of the mechanism of Rd increase, we took note of contaminant incorporation and of the relations between the device lifetime and the strength of the channel electric field. In the fabrication process, reducing contaminants, especially fluorine, significantly suppressed the increase of source and drain resistances. Cross-sectional views of the gate of improved devices, which had a long lifetime, confirmed an almost contaminant-free surface around the gate. In acceleration tests, the most negative impact on drain resistance stability among several bias conditions was found when the current density was high and the channel electric field was large at the same time. The dependence of drain-gate electric field strength E showed that the device lifetimes of HEMTs determined from Rd increase obeyed exp(1/E), which means that impact ionization was the main cause of degradation. We elucidate that the interactions of hot carriers with contaminants around the gate are the main causes of the Rd increase in HEMTs. Suppression of device degradation was achieved by optimizing the fabrication process around the gate. In this way, device lifetime was remarkably enhanced. 相似文献
8.
为准确评估硅IGBT和碳化硅MOSFET等高压大功率器件不同电应力及热应力条件下的栅极可靠性,研制了实时测量皮安级栅极漏电流的高温栅偏(high temperature gate bias,HTGB)测试装置。此外,该测试装置具备阈值电压在线监测功能,可以更好地监测被测器件的状态以进行可靠性评估和失效分析。为初步验证测试装置的各项功能和可靠性,运用该测试装置对商用IGBT器件在相同温度应力不同电应力条件下进行分组测试。初步测试结果表明老化初期漏电流逐渐降低,最终漏电流大小与电压应力有良好的正相关性,栅偏电压越大,漏电流越大。该测试装置实现了碳化硅MOSFET器件和硅IGBT器件对高温栅偏的测试需求且适用于各种类型的封装。 相似文献
9.
In this paper we present a comprehensive physical model that describes charge transport and degradation phenomena in high-k stacks. The physical mechanisms are modeled using a novel material-related approach that includes in a self-consistent fashion the charge transport (dominated by defect-assisted contribution), power dissipation and temperature increase, defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which play a crucial role in determining the electrical behavior of the high-k stacks, depend on their atomistic configurations, as calculated using ab-initio methods. This simulation framework represents a powerful tool to interpret electrical characterization measurements. In addition, it can be used to optimize logic and memory device stacks thanks to its predictive statistical capabilities that allow reproducing gate current, threshold voltage increase and time to breakdown (TDDB) statistics. Simulation results performed using this simulation package are shown to reproduce accurately leakage current, Stress-Induced Leakage Current (SILC), threshold voltage shift observed during Positive Bias Temperature Instability (PBTI) stress, TDDB in various dielectric stacks. 相似文献
10.
Neugroschel A. Bersuker G. Choi R. Byoung Hun Lee 《Device and Materials Reliability, IEEE Transactions on》2008,8(1):47-61
A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/HfO2/SiO2 gate stacks was investigated. Interface trap generation was assessed by the direct-current current-voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift (DeltaVTH). The metal/high-fc induced traps in the interfacial SiO2 layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of DeltaVTH and the stress-generated interface trap density DeltaDIT stress time dependencies. Similar kinetics of the long-term DeltaVTH(t) and DeltaDIT(t) dependencies in the high-fe and SiO2 gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO2 film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured DeltaVTH and DeltaDIT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate DeltaVTH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery. 相似文献
11.
高性能GaN常关型功率开关器件的实现是目前研究的热点。槽栅结构GaN常关型MOSFET以其栅压摆幅冗余度大、栅极漏电流小等优势受到广泛关注。制备槽栅结构GaN常关型MOSFET需要的刻蚀方法会在栅极沟道引入缺陷,影响器件的稳定性。首先,提出选择区域外延方法制备槽栅结构GaN常关型MOSFET,期望避免刻蚀对栅极沟道的损伤;再通过改进选择区域外延工艺(包括二次生长界面和异质结构界面的分离及抑制背景施主杂质),使得二次生长的异质结构质量达到标准异质结构水平。研究结果表明,选择区域外延方法能够有效保护栅极导通界面,使器件具备优越的阈值电压稳定性;同时也证明了选择区域外延方法制备槽栅结构GaN常关型MOSFET的可行性与优越性。 相似文献
12.
Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO2 interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO2 interface between source to drain region of the MOSFET and explained from analytical device physics perspectives. 相似文献
13.
A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results. 相似文献
14.
《Device and Materials Reliability, IEEE Transactions on》2009,9(4):516-523
15.
《Device and Materials Reliability, IEEE Transactions on》2009,9(2):237-243
16.
Saeed Uz Zaman Khan Md. Shafayat Hossain Fahim Ur Rahman Rifat Zaman Md. Obaidul Hossen Quazi D. M. Khosru 《International Journal of Numerical Modelling》2015,28(4):389-403
High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of InxGa1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 1023 m−3, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 1023 m−3, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd. 相似文献
17.
M. Aldegunde A. J. García-Loureiro K. Kalna A. Asenov 《Journal of Computational Electronics》2006,5(4):311-314
Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate
dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon
and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential
pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains
in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of
the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow.
At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage
the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the
25 nm gate length MOSFET. 相似文献
18.
Chia-Hua Chang Jenn-Gwo Hwu 《Device and Materials Reliability, IEEE Transactions on》2007,7(4):611-616
In this paper, the physical and electrical characteristics of low-temperature-processing hafnium oxide (HfO2) films are studied. A simple cost-effective room-temperature process was introduced to prepare high-k HfO2 dielectrics. A novel technique of direct oxidation of an ultrathin Hf metal by nitric acid, followed by rapid thermal annealing in N2 is demonstrated. The prepared HfO2 gate dielectrics show good uniformity, low leakage currents, high breakdown field, and superior reliability under electrical stressing. The long-term ten-year lifetime was also evaluated by a time-dependent-dielectric-breakdown analysis to project the maximum operation voltage of -1.8 V for HfO2 gate stacks. This low-temperature oxidation technology for preparing high-quality high-k HfO2 dielectrics is promising for flat-panel-display applications. 相似文献
19.
In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications. 相似文献
20.
Rishu Chaujar Ravneet Kaur Manoj Saxena Mridula Gupta R. S. Gupta 《International Journal of Numerical Modelling》2009,22(3):259-278
In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO2‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd. 相似文献