Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

A novel self-aligned TiN formation by N2+implantation during two-step annealing Ti-salicidation for submicrometerCMOS technology application

A new technology of self-aligned TiN/TiSi₂ formation using N₂⁺ implantation during two-step annealing Ti-salicidation process has been developed. The formation of TiN was confirmed by RBS analysis. The leakage currents of n⁺/p junction diodes fabricated using this technology were measured to investigate the phenomena of Al spiking into Si-substrate. The measured reverse-bias leakage current of diode per unit junction area with Al/TiN/TiSi₂ contact is 1.2 nA/cm² at -5 V, which is less than all of reported data. Also it can sustain the annealing process for 30 min at 500°C. Thus, TiN formed with this technology process is suggested as a very effective barrier layer between TiSi₂ and Al for submicron CMOS technology applications     

Strained-layer InGaAs-GaAs-AlGaAs lasers with monolithicallyintegrated photodiodes by selective-area MOCVD

Fabrication, design, and operation of strained layer, InGaAs-GaAs-AlGaAs lasers with monolithically integrated photodiodes fabricated by selective-area epitaxy are presented. Threshold currents as low as 8 mA (~300 A/cm²) were obtained for uncoated devices operating cw at room temperature. A responsivity of 71 μA/mW was obtained for a device with a photodiode etched facet angle of 3° and a photodiode bias of 0 V     

Nitrogen-implanted SiC diodes using high-temperature implantation

6H-SiC diodes fabricated using high-temperature nitrogen implantation up to 1000°C are reported. Diodes were formed by RIE etching a 0.8-μm-deep mesa across the N⁺/P junction using NF₃/O₂ with an aluminum transfer mask. The junction was passivated with a deposited SiO₂ layer 0.6 μm thick. Contacts were made to N⁺ and P regions with thin nickel and aluminum layers, respectively, followed by a short anneal between 900 and 1000°C. These diodes have reverse-bias leakage at 25°C as low as 5×10^-11 A/cm² at 10 V     

High mobility tri-layer a-Si:H thin-film transistors with ultrathinactive layer

We show that hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-μm channel length TFT, the linear region (V_DS=0.1 V) and saturation region mobilities increase from 0.4 cm²/V·s and 0.7 cm²/V·s for a 50-nm thick active layer a-Si:H device to 0.7 cm²/V·s and 1.2 cm²/V·s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing     

Enhancing the Near-Infrared Spectral Response of Silicon Optoelectronic Devices via Up-Conversion

A silicon-based optoelectronic device that exhibits an enhanced response to subbandgap light is described. The device structure consists of a bifacial silicon solar cell with an up- converting (UC) layer attached to the rear. Erbium-doped sodium yttrium fluoride (NaY_0.8F₄ : Er_0.2 ³⁺) phosphors are the optically active centers responsible for the UC luminescence. The unoptimized device is demonstrated to respond effectively to wavelengths (lambda) in the range of 1480-1580 nm with an external quantum efficiency (EQE) of 3.4% occurring at 1523 nm at an illumination intensity of 2.4 W/cm² (EQE = 1.4 times 10^-2 cm²/W). An analysis of the optical losses reveals that the luminescence quantum efficiency (LQE) of the device is 16.7% at 2.4 W/cm² of 1523-nm excitation (LQE = 7.0 times 10^-2 cm²/W), while further potential device improvements indicate that an EQE of 14.0% (5.8 times 10^-2 cm²/W) could be realistically achieved.     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

Strained layer (1.5 μm) InP/InGaAsP lasing opto-electronicswitch (LOES)

We present for the first time a lasing opto-electronic switch (LOES) fabricated in the InP/InGaAsP system. In this device the active region is composed of four 63 Å compressively strained quantum wells. A lasing threshold of 104 mA, or 6933 A/cm², has been observed at a temperature of 298 K, with an external differential quantum efficiency of 14%. The lasing wavelength is centered at 1.52 μm. The current-voltage characteristics manifest pronounced differential negative resistance, characterized by switching and holding voltages of 6.8 V and 1.6 V, respectively, and a switching current density of 33 A/cm². The OFF and ON state resistances are approximately 150 kΩ and 4 Ω, respectively     

Synthesis of polymers for hole and electron transport materials inorganic electroluminescent devices

Styrene-type polymers having tetraphenylbenzidine (TPD) or tetraphenylphenyldiaminobenzene unit (PDA) and a oxadiazole unit (PBD) on the side chain were prepared as hole and electron transport materials, respectively, of an electroluminescent (EL) device. The device structures employed were [indium-tin-oxide (ITO)/hole transport layer (HTL)/Al] (type I), or [ITO/hole transport layer (HTL)/electron transport layer (ETL)/Al] (type II). Type I devices provided current density higher than 100 mA/cm² but no luminescence was observed. Type II devices emitted luminescence of about 10 cd/m² at the current density of about 170 mA/cm². The emission maximums of these devices were 460 and 530 nm for the device using TPD and PDA, respectively     

3100 V, asymmetrical, gate turn-off (GTO) thyristors in 4H-SiC

A 2-mm×2-mm, 4H-SiC, asymmetrical npnp gate turn-off (GTO) thyristor with a blocking voltage of 3100 V and a forward current of 12 A is reported. This is the highest reported power handling capability of 37 kW for a single device in SiC. The 5-epilayer structure utilized a blocking layer that was 50 μm thick, p-type, doped at about 7-9×10¹⁴ cm^-3. The devices were terminated with a single zone junction termination extension (JTE) region formed by ion-implantation of nitrogen at 650°C. The device was able to reliably turn-on and turn-off 20 A (500 A/cm²) of anode current with a turn-on gain (I_K/I_{G, on}) of 20 and a turn-off gain (I_K/I_{G, off}) of 3.3     

Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

Electrical characteristics of 4.5 kV implanted anode 4H-SiC p-i-njunction rectifiers

4500 V 4H-SiC p-i-n junction rectifiers with low on-state voltage drop (3.3-4.2 V), low reverse leakage current (3×10^-6 A/cm²), and fast switching (30-70 ns) have been fabricated and characterized. Forward current-voltage measurements indicate a minimum ideality factor of 1.2 which confirms a recombination process involving multiple energy levels. Reverse leakage current exhibits a square root dependence on voltage below the punchthrough voltage where leakage currents of less than 3×10^-6 A/cm² are measured. Reverse recovery measurements are presented which indicate the presence of recombination at the junction perimeter where a surface recombination velocity of 2-8×10⁵ cm/s is found. These measurements also indicate drift layer bulk carrier lifetimes ranging from 74 ns at room temperature to 580 ns at 250°C     

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 10¹⁰cm^-2. The effective carrier mobility calculated from the drain conductance is 750 cm²/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V.     

Fabrication of planar optical waveguides in LiB3O5 by 2 MeV He+ ion implantation

The fabrication of planar optical waveguides in LiB₃O ₅ is discussed. Using 2-MeV ⁴He⁺ implantation with a dose of 1.5×10¹⁶ ions/cm² at 300 K, the refractive indexes of a 0.2-μm-thick layer 5.1 μm below the crystal surface are reduced to form optical barrier guides. For this ion dose the maximum change from the bulk values of refractive index at a wavelength of 0.488 μm are 1.5%, 5.25%, and 4% for n_x, n_y, and n_z, respectively. The refractive indexes of the guiding region change by less than 0.02% from the bulk values. The dose dependence of the optical barrier height has been measured. A threshold ion dose of about 0.75×10¹⁶ ions/cm² is required to form a refractive index barrier and ion doses higher than about 2.5×10¹⁶ ions/cm². saturate the refractive index decrease. Waveguide propagation losses for annealed single energy implants of dose 1.5×10¹⁶ ions/cm² are dominated by tunneling and are estimated to be ~8.9 dB/cm for the z-cut waveguides used. Multiple energy implants broaden the optical barrier, and losses of <4 dB/cm have been observed     

High-mobility modulation-doped SiGe-channel p-MOSFETs

A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n⁺ polysilicon gate, and p⁺ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm²/V-s at 300 K and 980 cm²/V-s at 82 K were achieved in functional submicrometer p-MOSFETs     

Quantum-well p-channel AlGaAs/InGaAs/GaAs heterostructureinsulated-gate field-effect transistors with very high transconductance

Quantum-well p-channel pseudomorphic AlGaAs/InGaAs/GaAs heterostructure insulated-gate field-effect transistors with enhanced hole mobility are described. The devices exhibit room-temperature transconductance, transconductance parameter, and maximum drain current as high as 113 mS/mm, 305 mS/V/mm, and 94 mA/mm, respectively, in 0.8-μm-gate devices. Transconductance, transconductance parameter, and maximum drain current as high as 175 mS/mm, 800 mS/V/mm, and 180 mA/mm, respectively were obtained in 1-μm p-channel devices at 77 K. From the device data hole field-effect mobilities of 860 cm²/V-s at 300 K and 2815 cm²/V-s at 77 K have been deduced. The gate current causes the transconductance to drop (and even to change sign) at large voltage swings. Further improvement of the device characteristics may be obtained by minimizing the gate current. To this end, a type of device structure called the dipole heterostructure insulated-gate field-effect transistor is proposed     

Avalanche phenomena in 4H-SiC p-n diodes fabricated by aluminum orboron implantation

Characteristics of p-n junction fabricated by aluminum-ion (Al⁺) or boron-ion (B⁺) implantation and high-dose Al⁺-implantation into 4H-SiC (0001) have been investigated. By the combination of high-dose (4×10¹⁵ cm^-2) Al⁺ implantation at 500°C and subsequent annealing at 1700°C, a minimum sheet resistance of 3.6 kΩ/□ (p-type) has been obtained. Three types of diodes with planar structure were fabricated by employing Al+ or B+ implantation. B ⁺-implanted diodes have shown higher breakdown voltages than Al⁺-implanted diodes. A SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 mΩcm² at room temperature. The diodes fabricated in this study showed positive temperature coefficients of breakdown voltage, meaning avalanche breakdown. The avalanche breakdown is discussed with observation of luminescence     

High brightness GaP green LED's

High brightness GaP green LED's have been developed by optimizing growth conditions to obtain a high quality p-n junction. In particular, the n-type GaP layer near the junction is greatly lowered in carrier concentration in order to decrease the nonradiative recombination center. The carrier concentration in the n-type GaP layer is decreased to 5-6 × 10¹⁵/cm³near the p-n junction and a minority-carrier lifetime of 800 ns (measured through the EL decay time) is obtained. The best device has a quantum efficiency of 0.45 percent at 12.5 A/cm^{2} with encapsulation. Excellent high-brightness LED lamps of 400 m Cd at a driving current of 20 mA can be obtained by using the high efficiency GaP green LED's.     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

1.54 lm GaSb/AlGaSb multi-quantum-well monolithic laser at 77 K grown on miscut Si substrate using interfacial misfit arrays

A GaSb quantum-well (QW) laser diode grown monolithically on a 5deg miscut Si (001) substrate is presented. The III-Sb epi-structure is grown monolithically on the miscut Si substrate via a thin (50 nm) AlSb nucleation layer. The 13% lattice mismatch between AlSb and Si is accommodated by a self-assembled 2D array of interfacial misfit dislocations (IMF). The 5deg miscut geometry enables simultaneous IMF formation and anti-phase domain suppression. The 1 mm times 100 mum GaSb QW laser diode operates under pulsed conditions at 77 K with a threshold current density of 2 kA/cm² and a maximum peak power of ~20 mW. Furthermore, the device is characterised by a 9.1 Omega forward resistance and a leakage current density of 0.7 A/cm² at -5 V.