A 3.4 dB NF k‐band LNA with a tapped capacitor matching network in 65 nm CMOS technology

This article proposes a tapped capacitor network for low‐noise amplifier (LNA) input matching which can provide much broader bandwidth than traditional ones. According to the design, the implemented LNA can realize noise match and power match simultaneously, which will broaden LNA's bandwidth without introducing larger noise than traditional ones. In addition, input pad parasitic capacitance can be absorbed by the network. Then a k‐band LNA with the matching network designed in 65 nm CMOS technology is shown to demonstrate the performance of the matching network. The tested results show that frequency band of S₁₁ less than ?10 dB is about 17 GHz and minimum NF is about 3.4 dB. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:146–153, 2015.     

A covering Ka‐band two‐way switch filter module using a three‐line and an E‐plane waveguide band‐pass filters

A millimeter‐wave ultrawideband two‐way switch filter module is presented in this article. The switch filter module covers whole Ka‐band (26–40 GHz), and is composed of two wideband band‐pass filters and two monolithic microwave integrated circuit (MMIC) single pole two throw (SP2T) switches. One filter is realized using E‐plane iris waveguide band‐pass filter, and another is realized by a novel 11‐pole three‐line microstrip structure band‐pass filter. Compared with the traditional three‐line filter, the proposed three‐line filter not only retains virtues of the traditional three‐line filter, but also resolves drawbacks of it, which include discontinuities between adjacent sections, many parameters of design, and no effective matching circuits at input/output ports. The developed switch filter module is fabricated using hybrid integrated technology, which has a size of 51 × 26 × 9.8 mm³, and interconnections between MMICs and microstrip are established by bond wires. The fabricated switch filter module exhibits excellent performances: for two different states, the measured insertion loss and return loss are all better than 7 and 10 dB in each pass‐band, respectively. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:305–310, 2015.     

RF MEMS,BST, and GaAs varactor system‐level response in complex modulation systems

This article presents the response of RF microelectromechanical systems (RF MEMS), barium strontium titanate (BST), and gallium arsenide (GaAs)‐based tunable filters and reconfigurable matching networks to a wideband code‐division‐multiple‐access signal centered at 1.95 GHz. The RF MEMS tunable filter and impedance tuner result in very low intermodulation distortion and spectral regrowth compared to their BST and GaAs counterparts. The linearity of the BST and GaAs tunable networks improves considerably by using a series combination of BST and GaAs varactors, but the RF MEMS‐based networks still show the best linearity of all three technologies. Also, it is shown that the reconfigurable networks, tuned with capacitive RF MEMS can handle up to 1 W of RF power with no self‐actuation. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008.     

Inductively‐loaded RF MEMS reconfigurable filters

This article presents an inductively loaded radio frequency (RF) microelectromechanical systems (MEMS) reconfigurable filter with spurious suppression implemented using packaged metal‐contact switches. Both simulation and measurement results show a two‐state, two‐pole 5% filter with a tuning range of 17% from 1.06 GHz to 1.23 GHz, an insertion loss of 1.56–2.28 dB and return loss better than 13 dB over the tuning range. The spurious passband response in both states is suppressed below ?20 dB. The unloaded Q of the filter changes from 127 to 75 as the filter is tuned from 1.06 GHz to 1.23 GHz. The design and full‐wave simulation of a two‐bit RF MEMS tunable filter with inductively loaded resonators and monolithic metal‐contact MEMS switches is also presented to prove the capability of applying the inductive‐loading technique to multibit reconfigurable filters. The simulation results for a two‐bit reconfigurable filter show 2.5 times improvement in the tuning range compared with the two‐state reconfigurable filter due to lower parasitics associated with monolithic metal‐contact MEMS switches in the filter structure. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Analysis and design of a fully integrated CMOS low‐noise amplifier for concurrent dual‐band receivers

This article thoroughly analyzes a concurrent dual‐band low‐noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual‐band LNA. As an example of the analysis, a fully integrated dual‐band LNA is designed in a standard 0.18‐μm 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high‐band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5‐V supply voltage and achieves voltage gains of 14 and 22 dB, input S₁₁ of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

A 60‐GHz single‐pole‐single‐throw switch in 65‐nm bulk CMOS

A single‐pole‐single‐throw (SPST) switch in a π‐network topology is designed in a 1.2‐V 65‐nm bulk CMOS RF process for millimeter‐wave applications in the 60‐GHz band from 57 to 66 GHz. The SPST switch with an active chip area of only 96 μm × 140 μm achieves the measured 11‐dB return loss, 1.6‐dB insertion loss, and 27.9‐dB isolation at 60 GHz. The SPST switch also shows the simulated power‐handling capability of 11.4 dBm and switching speed of 1 ns at 60 GHz. These results clearly demonstrate that the SPST switch in CMOS rivals the performance of SPST switches in GaAs and therefore has potential to be used in highly‐integrated 60‐GHz CMOS radios. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

Hybrid Ku‐band low‐noise amplifier for mobile DBS active phased‐array antennas

In this article we present a two‐stage Ku‐band low‐noise amplifier (LNA) using discrete pHEMT transistors on non‐PTFE substrates for low‐cost direct broadcast satellite (DBS) phased‐array systems (patent pending). The vertical input configuration of the LNA lends itself to direct integration with input port of antenna modules of the phased array, which minimizes preamplification losses. DC decoupling between LNA stages is realized using interdigital microstrip capacitors such that the implementation reduces the number of discrete microwave components and thereby not only reduces the component and assembly costs but also decreases the standard deviation of such crucial parameters of phased‐array systems as the end‐to‐end phase shift of the amplifier and the amplifier gain. Using the proposed printed decoupling capacitors, a cost reduction better than 30% of the original costs has been achieved. Additionally, we present a hybrid design procedure for the complete LNA, including its input and output connectors as well as packaging effects. This method is not based on parameter extraction, but encompasses electromagnetic (EM) field simulator results which are further combined using a high‐level circuit simulator. According to the presented measurement results, the implemented Ku‐band LNA has a noise figure better than 0.9 dB and a gain higher than 20 dB with a gain flatness of 0.3 dB over a 5% bandwidth. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

Systematic design of 7‐to‐40‐GHz on‐chip mixer based on optimal impedance deviation coefficient

In this article, a 7‐GHz to 40‐GHz ultra‐wideband passive double‐balanced mixer MMIC using compact wideband Marchand balun (CWMB) is presented. The CWMB is analyzed and designed by introducing a novel optimal impedance deviation coefficient. A trade‐off between the needed bandwidth and the acceptable insertion loss in an ultra‐wideband passive‐doubly‐balanced mixer design can be made through introducing the optimal impedance deviation coefficient. Finally, to verify the proposed methodology, a compact wideband passive double‐balanced mixer monolithic microwave integrated circuit (MMIC) was designed and fabricated using a standard gallium arsenide (GaAs) pHEMT technology according to the process characteristics. Experimental results show that an ultra‐wideband mixer MMIC is realized from 7 GHz to 40 GHz (140% fractional bandwidth) with a measured conversion loss between 9.5 dB~12.5 dB (in‐band fluctuation less than 3 dB) and a LO‐to‐RF isolation larger than 34 dB. The measurement results are in good agreement with the simulation results.     

18‐31 GHz GaN wideband low noise amplifier (LNA) using a 0.1 μm T‐gate high electron mobility transistor (HEMT) process

GaN technology has attracted main attention towards its application to high‐power amplifier. Most recently, noise performance of GaN device has also won acceptance. Compared with GaAs low noise amplifier (LNA), GaN LNA has a unique superiority on power handling. In this work, we report a wideband Silicon‐substrate GaN MMIC LNA operating in 18‐31 GHz frequency range using a commercial 0.1 μm T‐Gate high electron mobility transistor process (OMMIC D01GH). The GaN MMIC LNA has an average noise figure of 1.43 dB over the band and a minimum value of 1.27 dB at 23.2 GHz, which can compete with GaAs and InP MMIC LNA. The small‐signal gain is between 22 and 25 dB across the band, the input and output return losses of the MMIC are less than ?10 dB. The P_1dB and OIP3 are at 17 dBm and 28 dBm level. The four‐stage MMIC is 2.3 × 1.0 mm² in area and consumes 280 mW DC power. Compared with GaAs and InP LNA, the GaN MMIC LNA in this work exhibits a comparative noise figure with higher linearity and power handling ability.     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

A miniature coupled‐line‐based 3‐dB directional coupler using GaAs PHEMT process

A novel complementary‐conducting‐strip (CCS) coupled‐line (CL) design is proposed to achieve compact size by applying two‐dimensional layout and standard gallium‐arsenide (GaAs) thin‐film technology. To obtain high coupling and satisfy the design rules of GaAs process, mixed‐couple mechanism with edge and broadside coupling are also used. A CCS CL‐based Ka‐band 3‐dB directional coupler is fabricated using WIN 0.15‐μm GaAs pseudomorphic high electron mobility transistor technology. Experimental results show that the proposed directional coupler can cover the entire Ka‐band (26–40 GHz) with through and coupling of approximately 3.7 ± 0.25 dB, and isolation of better than 13 dB. In addition, the phase difference between the two output ports is approximately 90° ± 5°. The occupied area of the prototype (without I/O networks) is only 220 × 220 μm². © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:21–26, 2016.     

A straightforward design technique for narrowband multi‐stage low‐noise amplifiers with I/O conjugate match

Low‐noise amplifier (LNA) designers often struggle to simultaneously satisfy gain, noise, stability, and I/O matching requirements. In this article, a novel design technique, tailored for two‐stage low‐noise amplifiers, is presented. The proposed design method is completely deterministic and exploits inductive source degeneration to obtain a two‐stage LNA featuring perfect input and output match together with low noise figure (NF) and a pre‐determined gain, including stability analysis. A novel flowchart is provided together with the corresponding design chart that contains gain, matching, and stability information, therefore addressing all key figures‐of‐merit of a linear amplifier. The design chart is easily implementable in commercial Electronic Design Automation software, to aid designers in the difficult task of selecting the appropriate source degeneration inductor value. The noise performance, on the other hand, is the best possible since the matching networks are designed to provide the input of the two Field Effect Transistors with the optimum termination for noise. The design method is validated with two separate test vehicles operating respectively at Ka‐band (26.5‐31.5 GHz) and K‐band (20.0‐24.0 GHz). The realized Monolithic Microwave Integrated Circuits exhibit 18 dB gain for both versions, NF of 1.5 and 1.2 dB, respectively for the Ka‐band and K‐band version. Input and output matching are typically better than 12 and 15 dB.     

3GHz～5GHz CMOS超宽带低噪声放大器设计

提出了一个低噪声、高线性的超宽带低噪声放大器(UWB LNA).电路由窄带PCSNIM LNA拓扑结构和并联低Q负载结构组成,采用TSMC 0.18 μm RFCMOS工艺,并在其输入输出端引入了高阶带通滤波器.仿真结果表明,在1.8V直流电压下LNA的功耗约为10.6 mW.在3 GHz～5 GHz 的超宽带频段内,...     

10W CW broadband balanced limiter/LNA fabricated using MSAG MESFET process

This article presents the design and test data for a 10W broadband balanced limiter/LNA MMIC fabricated using MSAG MESFET process. The limiter is based on Schottky diodes and the two‐stage LNA is designed using high‐performance MESFETs. The typical measured performance for the limiter/LNA circuit includes gain greater than 14 dB, NF less than 2.7 dB, and return loss better than 20 dB over the 8.5–11.5 GHz frequency range. The CW power handling for the packaged limiter/LNA circuits was greater than 10W. The packaged devices were also exposed to power levels greater than 10W, and no catastrophic failures were observed up to 18W. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 13: 118–127, 2003.     

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g_m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.     

Miniaturized frequency‐agile bandpass filter integrated single‐pole double‐throw switch

This article presents a miniaturized frequency‐agile bandpass filter (BPF) integrated single pole double throw (SPDT) switch using common LC resonator. The BPF‐integrated on‐sate channel is constituted by the capacitively coupled LC resonators with loaded varactor diodes and reverse‐biased p‐i‐n diodes. The off‐state channel with high suppression is built when the p‐i‐n diodes loaded LC resonators is forward‐biased. As an example, a frequency‐agile BPF‐integrated SPDT switch with constant 3‐dB fractional bandwidth of 18.4% is designed. Its fabricated circuit area including bias circuit but excluding feeding lines is 0.105 λ_g × 0.079 λ_g. Measured results show that its 3 dB operating frequency bandwidth covers from 0.499 to 1.077 GHz with in‐band insertion loss varying from 4.15 to 3.15 dB. Off‐state suppression better than 37.8 dB, port‐to‐port isolation better than 51.1 dB, and good return loss can be also observed.     

A comparison of three‐dimensional electromagnetic and RC parasitic extraction analysis of mm‐wave on‐chip passives in SiGe BiCMOS low‐noise amplifiers

Layout parasitics significantly impact the performance of mm‐wave microelectronic circuits. These effects may be estimated by including foundry‐qualified pcell interconnect models in schematic with or without additional RC parasitics extraction (RCPE), or by generating an EM simulation (FEM and MoM) of the layout and cosimulating with active device models. In this paper, these methods are compared at by simulating the compression (P1db), gain (S₂₁), and noise figure (NF) of a V‐band LNA in 130 nm SiGe BiCMOS and comparing the results of different simulation approaches to measurements. It is found that the FEM cosimulated results agree better with the measurements than the other methods, providing a maximum error of 0.8 dB in gain, 0.18 dB in NF, and 0.6 dB in P1dB. This is a significant improvement over the errors obtained with pcell‐based schematic (2.6 dB in gain, 0.1 dB in NF, and 2.2 dB in P1db), schematic simulation with RCPE (1.55 dB in gain, 1.15 dB in NF, and 0.8 dB in P1db), and MoM cosimulation (0.67 dB in gain, 0.72 in NF, and 0.67 in P1db). This experiment validates the preference to FEM cosimulation in mm‐wave microelectronic circuits yet would indicate that reasonably accurate first‐iteration results may be obtained through a combined pcell‐RCPE approach with significantly shorter simulation time.     

Compact planar frequency reconfigurable multiple‐input‐multiple‐output antenna with pattern and polarization diversity characteristics for WiFi and WiMAX standards

A compact planar frequency reconfigurable dual‐band multiple‐input‐multiple‐output (MIMO) antenna with high isolation and pattern/polarization diversity characteristics is presented in this article for WiFi and WiMAX standards. The MIMO configuration incorporates two symmetrically placed identical antenna elements and covers overall size of 24 mm × 24 mm × 0.762 mm. Reconfiguration of each antenna element is achieved by using a PIN diode which allows antennas to switch from state‐1 (2.3‐2.4 GHz and 4.6‐5.5 GHz) to state‐2 (3.3‐3.5 GHz and 4.6‐5.5 GHz). In state‐1, the configuration offers isolation ≥18 dB and 20 dB in lower band (LB) and upper band (UB) respectively; whereas, in state‐2, isolation ≥21 dB and 20 dB in LB and UB respectively is achieved. The same decoupling circuit provides high isolation in dual‐band of two states, which makes overall size of the proposed design further compact. The antennas are characterized in terms of envelope correlation coefficient, radiation pattern, gain, and efficiency. From measured and simulated results, it is verified that the proposed frequency reconfigurable dual‐band multi‐standard MIMO antenna design shows desirable performance in both operating bands of each state and compact size of the design makes it suitable for small form factor devices used in future wireless communication systems.     

An unbalanced‐to‐balanced diplexer based on substrate integrated waveguide cavity

A novel unbalanced‐to‐balanced diplexer based on a dual‐mode substrate integrated waveguide (SIW) cavity is proposed and implemented. The diplexer is realized using one dual‐mode cavity and two single‐mode cavities. By properly choosing, feeding and coupling the cavity operating at the TE₁₀₂ or TE₂₀₁ mode, so as to not only provide capabilities to realize the desired unbalanced‐to‐balanced transmission within both Rx and Tx channels but also realize good differential‐mode channel‐to‐channel isolation. To the author's knowledge, we present for the first time an unbalanced‐to‐balanced type diplexer based on the application of SIW. The proposed diplexer was successfully designed, simulated, and fabricated. Good agreement can be observed between simulated and measured performances in our letter. The measured in‐band common‐mode rejection is better than 33 dB for both channels. A minimum differential‐mode isolation of about 50 dB across the Rx band and about 40 dB across the Tx band is also observed in the measurement. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:173–177, 2015.     

Stability investigation for InP DHBT mm‐wave power amplifier

In this article, we discuss stability issues for mm‐wave monolithic integrated power amplifiers using InP double heterojunction bipolar transistor (DHBT) technology targeting E‐band applications at 71–76 GHz and 81–86 GHz. Different stability detection methods based on the classical two‐port K‐Δ_s pair, linear three‐port graphical analysis, system identifications, circuit modal analysis, and normalized determinant function are all reviewed. The corresponding techniques are employed to predict the occurrence of instability at 15 GHz observed during measurements on a fabricated monolithic microwave integrated circuit power amplifier. Experimental results from a redesigned power amplifier with improved stability are presented to confirm that the previously detected oscillation loop is removed using odd‐mode stabilization resistors with the correct choice of values and locations. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE 23: 662–674, 2013.