Oxide-silicon-oxide buffer structure for ultralow temperature polycrystalline silicon thin-film transistor on plastic substrate

A novel oxide-silicon-oxide buffer structure to prevent damage to a plastic substrate in an ultralow temperature (<120/spl deg/C) polycrystalline silicon thin-film transistor (ULTPS TFT) process is presented. Specifically, an amorphous silicon film was inserted as an absorption layer into buffer oxide films. The maximum endurable laser energy was increased from 200 to 800 mJ/cm/sup 2/. The fabricated ULTPS nMOS TFT showed a performance with mobility of 30 cm/sup 2//Vs.     

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.     

Si/SiGe n-MODFETs on thin SiGe virtual substrates prepared by means of He implantation

Si/SiGe n-type modulation-doped field-effect transistors grown on a very thin strain-relieved Si/sub 0.69/Ge/sub 0.31/ buffer on top of a Si(100) substrate were fabricated and characterized. This novel type of virtual substrate has been created by means of a high dose He ion implantation localized beneath a 95-nm-thick pseudomorphic SiGe layer on Si followed by a strain relaxing annealing step at 850/spl deg/C. The layers were grown by molecular beam epitaxy. Electron mobilities of 1415 cm/sup 2//Vs and 5270 cm/sup 2//Vs were measured at room temperature and 77 K, respectively, at a sheet carrier density of about 3/spl times/10/sup 12//cm/sup 2/. The fabricated transistors with Pt-Schottky gates showed good dc characteristics with a drain current of 330 mA/mm and a transconductance of 200 mS/mm. Cutoff frequencies of f/sub t/=49 GHz and f/sub max/=95 GHz at 100 nm gate length were obtained which are quite close to the figures of merit of a control sample grown on a conventional, thick Si/sub 0.7/Ge/sub 0.3/ buffer.     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

High-performance ultralow-temperature polycrystalline silicon TFT using sequential lateral solidification

This letter presents technologies to fabricate ultralow-temperature (< 150 /spl deg/C) polycrystalline silicon thin-film transistor (ULTPS TFT). Sequential lateral solidification is used for crystallization of RF magnetron sputter deposited amorphous silicon films resulting in a high mobility polycrystalline silicon (poly-Si) film. The gate dielectric is composed of plasma oxidation and Al/sub 2/O/sub 3/ grown by plasma-enhanced atomic layer deposition. The breakdown field on the poly-Si film was above 6.3 MV/cm. The fabricated ULTPS TFT showed excellent performance with mobility of 114 cm/sup 2//V /spl middot/ s (nMOS) and 42 cm/sup 2//V /spl middot/ s (pMOS), on/off current ratio of 4.20 /spl times/ 10/sup 6/ (nMOS) and 5.7 /spl times/ 10/sup 5/ (pMOS), small V/sub th/ of 2.6 V (nMOS) and -3.7 V (pMOS), and swing of 0.73 V/dec (nMOS) and 0.83 V/dec (pMOS).     

Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively.     

Poly-Si TFT Fabricated at 150 deg C Using ICP-CVD and Excimer Laser Annealing

We fabricated poly-Si thin-film transistors at 150/spl deg/C using inductively coupled plasma (ICP) chemical vapor deposition (CVD) and excimer laser annealing (ELA). An Si film deposited by ICP-CVD was recrystallized using ELA, and a poly-Si film with large grains exceeding 5000 /spl Aring/ in diameter was fabricated. An SiO/sub 2/ film with a high breakdown field was deposited by ICP-CVD. A high mobility exceeding 100 cm/sup 2//Vs and a low subthreshold swing of 0.76 V/dec were successfully achieved.     

High mobility nanocrystalline silicon transistors on clear plastic substrates

We demonstrate nanocrystalline silicon (nc-Si) top-gate thin-film transistors (TFTs) on optically clear, flexible plastic foil substrates. The silicon layers were deposited by plasma-enhanced chemical vapor deposition at a substrate temperature of 150/spl deg/C. The n-channel nc-Si TFTs have saturation electron mobilities of 18 cm/sup 2/V/sup -1/s/sup -1/ and transconductances of 0.22 /spl mu/S/spl mu/m/sup -1/. With a channel width to length ratio of 2, these TFTs deliver up to 0.1 mA to bottom emitting electrophosphorescent organic light-emitting devices (OLEDs) which were fabricated on a separate glass substrate. These results suggest that high-current, small-area OLED driver TFTs can be made by a low-temperature process, compatible with flexible clear plastic substrates.     

A novel four-mask-processed poly-Si TFT fabricated using excimer laser crystallization of an edge-thickened a-Si active island

A four-mask-processed polycrystalline silicon thin-film transistor (poly-Si TFT) is fabricated using 50-pulse KrF excimer laser to crystallize an edge-thickened amorphous silicon (a-Si) active island without any shrinkage. This method introduces a temperature gradient in the island to enlarge grains from the edge, especially when the channel width is narrow. The grain boundaries across the width of the channel suppress the leakage current and the drain-induced barrier lowering. Moreover, the proposed poly-Si TFT with a channel length of L = 2 /spl mu/m and a channel width of W = 1.2 /spl mu/m possesses a high field-effect mobility of 260 cm/sup 2//Vs and an on/off current ratio of 2.31 /spl times/ 10/sup 8/.     

Fully silicided NiSi:Hf-LaAlO/sub 3//SG-GOI n-MOSFETs with high electron mobility

We have integrated the low work function NiSi:Hf gate on high-/spl kappa/ LaAlO/sub 3/ and on smart-cut Ge-on-insulator (SC-GOI) n-MOSFETs. At 1.4-nm equivalent oxide thickness, the NiSi:Hf-LaAlO/sub 3//SC-GOI n-MOSFET has comparable gate leakage current with the control Al gate on LaAlO/sub 3/-Si MOSFETs that is /spl sim/5 orders of magnitude lower than SiO/sub 2/. In addition, the LaAlO/sub 3//SC-GOI n-MOSFET with a metal-like fully NiSi:Hf gate has high peak electron mobility of 398 cm/sup 2//Vs and 1.7 times higher than LaAlO/sub 3/-Si devices.     

Implementation of fully self-aligned bottom-gate MOS transistor

This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 /spl mu/m are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm/sup 2//V-s, off-current of 0.17 pA//spl mu/m, and on-off current ratio of 7.1/spl times/10/sup 8/.     

Performance of polysilicon gate HfO/sub 2/ MOSFETs on [100] and [111] silicon substrates

Mobility dependence on Si substrate orientations was investigated for HfO/sub 2/ MOSFETs for the first time. High-temperature (600 /spl deg/C) forming gas (FG) annealing (HT-FGA) was applied on the devices on both [100] and [111] substrates to evaluate the mobility for optimal interfacial quality. Using HT-FGA, D/sub it/ of the [111] devices was reduced down below 1 /spl times/ 10/sup 12/ cm/sup -2/V/sup -1/. Similar to SiO/sub 2/ devices, NMOS mobility of the [111] devices was lower than that of the [100] devices at higher effective fields, while it was reversed for PMOSFETs.     

Self-aligned amorphous-silicon TFTs on clear plastic substrates

We fabricated the first bottom-gate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a clear plastic substrate with source and drain self-aligned to the gate. The top source and drain are self-aligned to the bottom gate by backside exposure photolithography through the plastic substrate and the TFT tri-layer. The a-Si:H channel in the tri-layer is made only 30 nm thick to ensure high optical transparency at the exposure wavelength of 405 nm. The TFTs have a threshold voltage of /spl sim/3 V, subthreshold slope of /spl sim/0.5 V/dec, linear mobility of /spl sim/1 cm/sup 2/V/sup -1/ s/sup -1/, saturation mobility of /spl sim/0.8 cm/sup 2/V/sup -1/s/sup -1/, and on/off current ratio of >10/sup 6/. These results show that self-alignment by backside exposure provides a solution to the fundamental challenge of making electronics on plastics: overlay misalignment.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

Anodic Oxidation of Si in Oxygen/Chlorine Plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO/sub 2/ interface was reduced from 7 X 10/sup 11//cm/sup 2//spl dot/eV to 5 X 10/sup 11//cm/sup 2/ /spl dot/eV at the midgap of Si; after annealing at 800/spl deg/C in argon for 60 min, it was reduced to 8 X 10/sup 10//cm/sup 2//spl dot/eV, and did not return to the original value after heating the specimen to 800/spl deg/C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasma-anodic SiO/sub 2/ films was reduced by annealing them at 800/spl deg/C in argon, but SiO/sub 2/ films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.     

High-performance poly-Si TFTs on plastic substrates using a nano-structured separation layer approach

We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable "mother" substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm/sup 2//V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A//spl mu/m-channel-width at V/sub ds/=-0.1 V, sub-V/sub t/ swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V.     

High-performance poly-Si TFTs made by Ni-mediated crystallization through low-shot laser annealing

High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been fabricated using metal-induced crystallization followed by laser annealing (L-MIC). Laser annealing after MIC was found to yield a major improvement to the electrical characteristics of poly-Si TFTs. At a laser fluence of 330 mJ/cm/sup 2/, the field effect mobility increased from 71 to 239 cm/sup 2//Vs, and the minimum leakage current reduced from around 3.0/spl times/10/sup -12/ A//spl mu/m to 2.9/spl times/10/sup -13/ A//spl mu/m at a drain voltage of 5 V. In addition, the dependence of the TFT characteristics on the laser energy density was much weaker than that for conventional excimer laser annealed poly-Si TFTs.