Single‐Electron Pass‐Transistor Logic with Multiple Tunnel Junctions and Its Hybrid Circuit with MOSFETs

To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single‐electron pass‐transistor logic circuit employing a multiple‐tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single‐electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3‐MTJ inverter circuit is simulated at 15 K with parameters C_g=C_T=C_clk=1 aF, R_T=5 MΩ, V_clk=40 mV, and V_in=20 mV. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ‐SETD logic is successfully translated to the voltage state logic.     

High temperature current–voltage characteristics of InP‐based tunnel junctions

In this paper, we present temperature‐dependent current–voltage measurements of tunnel junctions lattice matched to InP at temperatures ranging from room temperature to 220 °C. Temperature‐dependent tunneling properties were extracted by fitting the current–voltage characteristics using a simple analytical formula. Three different designs of tunnel junction were characterized, including a bulk InAlGaAs tunnel junction, an InAlGaAs tunnel junction with InAlAs cladding layers and an InGaAs/InAlGaAs quantum‐well tunnel junction. Each device exhibited different temperature dependence in peak tunnel current and excess current, with the quantum‐well tunnel junction exhibiting the greatest temperature sensitivity. We use a non‐local tunneling model, in conjunction with a numerical drift‐diffusion solver, to explain the performance improvement available by using double heterostructure cladding layers around the junction region, and use the same model to explain the observed temperature dependence of the devices. Copyright © 2014 John Wiley & Sons, Ltd.     

Core–Shell ZnxCd1?xSe/ZnyCd1?ySe Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn _y Cd_1−y Se-cladded Zn _x Cd_1−x Se quantum dots (y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn _y Cd_1−y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II–VI quantum dots as well as two diverse types of devices are presented in this paper.     

Interlayer Band‐to‐Band Tunneling and Negative Differential Resistance in van der Waals BP/InSe Field‐Effect Transistors

Atomically thin layers of van der Waals (vdW) crystals offer an ideal material platform to realize tunnel field‐effect transistors (TFETs) that exploit the tunneling of charge carriers across the forbidden gap of a vdW heterojunction. This type of device requires a precise energy band alignment of the different layers of the junction to optimize the tunnel current. Among 2D vdW materials, black phosphorus (BP) and indium selenide (InSe) have a Brillouin zone‐centered conduction and valence bands, and a type II band offset, both ideally suited for band‐to‐band tunneling. TFETs based on BP/InSe heterojunctions with diverse electrical transport characteristics are demonstrated: forward rectifying, Zener tunneling, and backward rectifying characteristics are realized in BP/InSe junctions with different thickness of the BP layer or by electrostatic gating of the junction. Electrostatic gating yields a large on/off current ratio of up to 10⁸ and negative differential resistance at low applied voltages (V ≈ 0.2 V). These findings illustrate versatile functionalities of TFETs based on BP and InSe, offering opportunities for applications of these 2D materials beyond the device architectures reported in the current literature.     

Current transport studies of amorphous n/p junctions and its application in a‐Si:H/HIT‐type tandem cells

This paper presents an understanding of the fundamental carrier transport mechanism in hydrogenated amorphous silicon (a‐Si:H)‐based n/p junctions. These n/p junctions are, then, used as tunneling and recombination junctions (TRJ) in tandem solar cells, which were constructed by stacking the a‐Si:H‐based solar cell on the heterojunction with intrinsic thin layer (HIT) cell. First, the effect of activation energy (E_a) and Urbach parameter (E_u) of n‐type hydrogenated amorphous silicon (a‐Si:H(n)) on current transport in an a‐Si:H‐based n/p TRJ has been investigated. The photoluminescence spectra and temperature‐dependent current–voltage characteristics in dark condition indicates that the tunneling is the dominant carrier transport mechanism in our a‐Si:H‐based n/p‐type TRJ. The fabrication of a tandem cell structure consists of an a‐Si:H‐based top cell and an HIT‐type bottom cell with the a‐Si:H‐based n/p junction developed as a TRJ in between. The development of a‐Si:H‐based n/p junction as a TRJ leads to an improved a‐Si:H/HIT‐type tandem cell with a better open circuit voltage (V_oc), fill factor (FF), and efficiency. The improvements in the cell performance was attributed to the wider band‐tail states in the a‐Si:H(n) layer that helps to an enhanced tunneling and recombination process in the TRJ. The best photovoltage parameters of the tandem cell were found to be V_oc = 1430 mV, short circuit current density = 10.51 mA/cm², FF = 0.65, and efficiency = 9.75%. Copyright © 2015 John Wiley & Sons, Ltd.     

Can Thermotunneling Improve the Currently Realized Thermoelectric Conversion Efficiency?

In a tunnel junction, electrons can overcome a nanoscale vacuum gap after the application of an electrical voltage. A temperature difference rather than an electrical voltage applied at the junction gives rise to an analogous thermoelectric tunnel effect called thermotunneling. This effect opens the possibility of thermoelectric conversion without phononic thermal backflow, which has encouraged optimism regarding the potential of thermotunneling for power generation and refrigeration. However, thermotunneling implies a photonic thermal backflow caused by radiative heat exchange amplified by photon tunneling of evanescent modes. An investigation based on a free electron model and comprising the combined influence of both electronic and photonic heat transfer through a vacuum tunnel gap is presented. An upper limit M = π ²/12 on the dimensionless thermoelectric figure of merit practically attainable by thermotunneling can be stated. This means that thermo- tunneling cannot outperform the maximum M values achieved by thermoelectric materials research to date.     

Photoinduced Contact Evolution and Junction Rearrangement in Two-Dimensional van der Waals Heterostructure

Devices based on 2DMs van der Waals (vdW) heterostructures always compose of multiple contacts. Due to the instability of nanoscale 2DMs and interfaces, these contacts can be affected by the operation-induced photo or thermal effect. They can trigger the evolution of junctions and rearrange the junctions across a device, which are detrimental for applications. Herein, vdW heterostructure of indium selenide (InSe) and black phosphorus (BP) on Au electrodes are investigated to reveal the contact evolution and its relation to device performance. During operation, light irradiation changes the I–V characteristics from symmetry to strong rectification. Photocurrent mapping and Kelvin-probe force microscopy (KPFM) reveal triple junctions in this heterostructure, i.e., Au-InSe junction, InSe homojunction, and InSe-BP heterojunction. The variation of I–V characteristics of vdW heterostructure is ascribed to the evolution of Au-InSe junction from quasi-ohmic junction with a near-zero work function difference (Δφ) to a strong Schottky junction (Δφ = ≈0.27 eV). The stabilized device demonstrates distinguished time-domain response at individual junctions and overall device, indicating the evolution of contacts and the consequent opposite junction directions degrade the overall device performance. This research emphasizes the importance of dealing with heterogeneous contacts and junction directions in designing vdW heterostructure photodetectors.     

A superconducting tunnel junction receiver for 345 GHz

In this paper we discuss the design, fabrication, and testing of a quasiparticle tunnel junction receiver for use at 345 GHz. The design employs small area Nb/Nb-oxide/PbInAu edge junctions in order to keep the device capacitance small and maintain a modest value for ωR_NC. For optimura noise performance and beam properties the mixer is contained in a waveguide mounting structure. Our best sensitivity was obtained at 312 GHz where we measured a double sideband (DSB) noise temperature of 275 K. Noise temperatures of 400 K (DSB) or better were obtained out to 350 GHz.     

A study of GaAs: Si/GaAs: C tunnel diodes grown by MOCVD

Technological modes in which high-efficiency GaAs: Si/GaAs: C tunneling structures can be fabricated by MOS-hydride epitaxy have been determined. It was demonstrated that use of C and Si dopants makes it possible to obtain a p-n junction with low diffusion spreading of dopant profiles. It was shown that fabrication of high-efficiency tunnel diodes requires that GaAs layers should be doped with acceptor and donor impurities to a level of ∼9 × 10¹⁹ cm⁻³. Tunnel diodes were fabricated using the tunnel structures and their current-voltage characteristics were studied. Peak current densities J _p ≈ 1.53 kA cm⁻² and a differential resistance R ≈ 30 mΩ under a reverse bias were obtained in the tunnel diodes.     

Anti‐Ferromagnet Controlled Tunneling Magnetoresistance

The requirement for high‐density memory integration advances the development of newly structured spintronic devices, which have reduced stray fields and are insensitive to magnetic field perturbations. This could be visualized in magnetic tunnel junctions incorporating anti‐ferromagnetic instead of ferromagnetic electrodes. Here, room‐temperature anti‐ferromangnet (AFM)‐controlled tunneling anisotropic magnetoresistance in a novel perpendicular junction is reported, where the IrMn AFM stays immediately at both sides of AlO_x tunnel barrier as the functional layers. Bi‐stable resistance states governed by the relative arrangement of uncompensated anti‐ferromagnetic IrMn moments are obtained here, rather than the traditional spin‐valve signal observed in ferromagnet‐based tunnel junctions. The experimental observation of room‐temperature tunneling magnetoresistance controlled directly by AFM is practically significant and may pave the way for new‐generation memories based on AFM spintronics.     

Controllable Switching between Highly Rectifying Schottky and p–n Junctions in an Ionic MoS2 Device

Semiconductor junctions are of great significance for the development of electronic and optoelectronic devices. Here, controllable switching is demonstrated from a Schottky junction to a p–n junction in a partially ionic liquid-gated MoS₂ device with two types of metal contacts. Excellent rectification behavior with a current on-off ratio exceeding 10⁶ is achieved in both Schottky and p–n junction modes. The formation of Schottky junction at the Pd electrode/MoS₂ contact and p–n junction at the p-MoS₂/n-MoS₂ interface is revealed by spatially resolved photocurrent mappings. The switching between the two junctions under ionic gate modulation is correlated with the evolution of the energy band, further validated by the finite element simulation. The device exhibits excellent photodetection properties in the p–n junction mode, including an open circuit voltage up to 0.84 V, a responsivity of 0.24 A W⁻¹, a specific detectivity of 1.7 × 10¹¹ Jones, a response time of hundreds of microseconds and a linear dynamic range of up to 91 dB. The electric field control of such high-performance Schottky and p–n junctions opens up fresh perspectives for studying the behavior of junction and the development of 2D electronic devices.     

Chemical Vapor Deposition of <Emphasis Type="Italic">α</Emphasis>-Boron Layers on Silicon for Controlled Nanometer-Deep <Emphasis Type="Italic">p</Emphasis><Superscript>+</Superscript><Emphasis Type="Italic">n</Emphasis> Junction Formation

Nanometer-thick amorphous boron (α-B) layers were formed on (100) Si during exposure to diborane (B₂H₆) in a chemical vapor deposition (CVD) system, either at atmospheric or reduced pressures, at temperatures down to 500°C. The dependence of the growth mechanism on processing parameters was investigated by analytical techniques, such as transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS), in conjunction with extensive electrical characterization. In particular, devices fabricated by B deposition effectively demonstrated that p ⁺ doping of the silicon substrate can be achieved within 10 nm from the surface in a manner that is finely controlled by the B₂H₆ exposure conditions. High-quality, extremely ultrashallow, p ⁺ n junctions were fabricated, and their saturation current was tuned from high Schottky-like values to low deep pn junction-like values by the increasing of the deposited B layer thickness. This junction formation exhibited high selectivity, isotropy, spatial homogeneity, and compatibility with standard Si device fabrication.     

Electromigration study of SNS ramp edge Josephson junctions

We report on the effects of electromigration of basal plane oxygen vacancies on SNS ramp edge Josephson junctions where the N-layer is YBa₂Cu_2.79Co_0.21O_7−δ, a doped version of the YBCO electrodes. Through the application of a 4–10 mA (∼2–5 MA/cm²) current bias at room temperature, the basal plane oxygen order and content in the N and S layers were improved. This is demonstrated by an increase in I_cR_n from <5 μV, to as much as 205 μV. The implications of these results on SNS junction fabrication, and the nature of tunneling in such devices are discussed.     

Classification of Energy Levels in Quantum Dot Structures by Depleted Layer Spectroscopy

The coexistence of quantum confined energy levels and defect energy levels in quantum dot (QD) structures may cause difficulties in distinguishing between their different origin when using deep-level transient spectroscopy (DLTS). Using InAs/GaAs QDs as demonstration vehicles, we present methodologies to obtain such a classification by DLTS. QD-related spectra measured as a function of repetition frequency of electrical pulses, f, or temperature, T, and reverse voltage, V _R, are depicted as contour plots on (f, V _R) and (T, V _R) planes, thus reflecting the complex thermal and tunneling emission of electrons from the ground and excited states. Defect-related levels give rise to different contour patterns and undergo modification, exhibiting double-peak structured emission when defects are agglomerated in the vicinity of the QD plane. This effect is interpreted in terms of an interaction between electron states in traps and the confined QD states.     

Dopant atoms as quantum components in silicon nanoscale devices

Recent progress in nanoscale fabrication allows many fundamental studies of the few dopant atoms in various semiconductor nanostructures. Since the size of nanoscale devices has touched the limit of the nature, a single dopant atom may dominate the performance of the device. Besides, the quantum computing considered as a future choice beyond Moore's law also utilizes dopant atoms as functional units. Therefore, the dopant atoms will play a significant role in the future novel nanoscale devices. This review focuses on the study of few dopant atoms as quantum components in silicon nanoscale device. The control of the number of dopant atoms and unique quantum transport characteristics induced by dopant atoms are presented. It can be predicted that the development of nanoelectronics based on dopant atoms will pave the way for new possibilities in quantum electronics.     

Effects of AsH3 surface treatment for the improvement of ultra-shallow area-selective regrown GaAs sidewall tunnel junction

Low-temperature (290°C) area-selective regrowth by molecular layer epitaxy (MLE) was applied for the fabrication of an ultra-shallow sidewall (50 nm) GaAs tunnel junction. Fabricated tunnel junctions have shown a record peak current density up to 35,000 A/cm². It is shown that the tunnel junction characteristics are strongly dependent on the sidewall orientation and the AsH₃ surface treatment conditions just prior to regrowth. The effects of AsH₃ surface treatment are discussed in view of the control of surface stoichiometry.     

Low-field current transport mechanisms in rf magnetron sputter deposited boron carbide (B5C)/p-type crystalline silicon junctions in the dark

Measurements of the forward and reverse currents in an undoped rf magnetron sputter deposited boron carbide (B₅C)/p-type Si(111) junction have been made in the dark in the temperature range 120–300K at low-bias voltages (0–0.3V). A diode-like behaviour of the junction current has been observed in this low-bias region at all temperatures but with a rather large reverse (leakage) current I _R, particularly at high temperatures (I _R≈2 μA at V = ?0:3V and T = 290 K). The forward ‘voltage factor’ A (T) was found to decrease with increasing temperature as A (T)≈q/ηk _B T, with relatively high values of the ‘ideality factor’ η(about 3.5–4), probably due to the existence of an interfacial layer. The temperature dependence of the measured junction current (forward and reverse) flowing at low bias voltages and of the forward ‘current factor’ I _0F can be described satisfactorily by a model of the tunnelling of thermally excited carriers, including tunnelling via impurity localized levels, of the form I (T) ∝ exp [?C/T ^1/3] over the entire temperature range studied (120–300K). A high density of ‘localized’ energy states as large as 10¹⁸ cm^?3 eV^?1 was estimated, which can be attributed in part to ‘extrinsic’ interface states that could have been formed throughout the fabrication procedures of the rf sputter deposited B₅C/p-crystalline silicon junction studied. Another possible cause of such large concentration of ‘localized’ states is the ‘intrinsic’ interface states produced by the lattice mismatch between the polycrystalline boron carbide and crystalline silicon semiconductors as well as of the high intrinsic defect concentration caused by structural imperfections that often exist in boron carbide compounds.     

Importance of the choice of the profile model for ap-n junction in the location of deep levels

The energy levels introduced by Pt in silicon have been measured in a non-abruptp ⁺-n junction using constant-capacitance thermal-emission rate measurements and a numerical simulation of high frequency-capacitance. Two levels have been detected with activation energies of:E _c -E _T = 0.22 eV with acceptor character andE _T -E _v = 0.34 eV with donor character. The sample preparation and diffusion of Pt is similar to previous works in which an acceptor levelE _c -E _T = 0.34 eV was found instead of or besides a donorlike levelE _T -E _v = 0.34 eV. Our numerical calculation of the shallow-impurity profile points to the existence of a gradual transition near the metallurgical junction for these samples. We have demonstrated that the well-known model of an abrupt junction is not appropriate for these types of junctions, and could lead to errors in the location attributed to the detected levels. Simulation of the electrical behavior leads to the non-existence of the acceptor levelE _c −E _T = 0.34 eV located in then-side of the junction.     

Nonvolatile Silicon Memory Using GeO<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>-Cladded Ge Quantum Dots Self-Assembled on SiO<Subscript>2</Subscript> and Lattice-Matched II–VI Tunnel Insulator

This paper presents fabrication and characterization of a quantum dot-based floating gate nonvolatile memory device with site-specific self-assembly of germanium oxide-cladded germanium (GeO _x -Ge) quantum dots on SiO₂ and ZnS/ZnMgS/ZnS (II–VI lattice-matched high-κ dielectric) tunnel insulator material. These monodispersed and individually cladded quantum dots have the potential to store charge uniformly in the floating gate and are well suited for nonvolatile memory applications.     

Shallow-Etch Mesa Isolation of Graded-Bandgap “W”-Structured Type II Superlattice Photodiodes

Shallow-etch mesa isolation (SEMI) of graded-bandgap “W”-structured type II superlattice (GGW) infrared photodiodes provides a powerful means for reducing excess dark currents due to surface and bulk junction related processes, and it is particularly well suited for focal-plane array fabrication. In the n-on-p GGW photodiode structure the energy gap is increased in a series of steps from that of the lightly p-type infrared-absorbing region to a value typically two to three times larger. The wider gap levels off about 10 nm short of the doping-defined junction, and continues for another 0.25 μm into the heavily n-doped cathode before the structure is terminated by an n ⁺-doped InAs top cap layer. The increased bandgap in the high-field region near the junction helps to strongly suppress both bulk tunneling and generation–recombination (G–R) current by imposing a much larger tunneling barrier and exponentially lowering the intrinsic carrier concentration. The SEMI approach takes further advantage of the graded structure by exposing only the widest-gap layers on etched surfaces. This lowers surface recombination and trap-assisted tunneling in much the same way as the GGW suppresses these processes in the bulk. Using SEMI, individual photodiodes are defined using a shallow etch that typically terminates only 10 nm to 20 nm past the junction, which is sufficient to isolate neighboring pixels while leaving the narrow-gap absorber layer buried 100 nm to 200 nm below the surface. This provides for separate optimization of the photodiode’s electrical and optical area. The area of the junction can be reduced to a fraction of that of the pixel, lowering bulk junction current, while maintaining 100% optical fill factor with the undisturbed absorber layer. Finally, with the elimination of deep, high-aspect-ratio trenches, SEMI simplifies array fabrication. We report herein results from SEMI-processed GGW devices, including large-area discrete photodiodes, mini-arrays, and a focal-plane array. Current–voltage data show strong suppression of side-wall leakage relative to that for more deeply etched devices, as well as scaling of dark current with junction area without loss of quantum efficiency.