Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

FVF‐Based Low‐Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop‐out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65‐nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).     

Substrate-connected high voltage pumping circuits for low supplyvoltages

Novel high voltage pumping circuits for low supply voltages are proposed. Utilising a small pumping circuit and the new substrate-connected techniques can enhance charge transfer efficiency and eliminate the body effect at low supply voltages. Furthermore, a diode-connected transistor technique can improve the reverse charge sharing phenomenon when the output has a load current. With this technique high boosted voltages can be obtained at low supply voltages     

一种动态补偿、高稳定性的LDO设计

设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面...     

一种应用于MEMS麦克风偏置电路的电荷泵设计

MEMS麦克风需要一个高于10 V的偏置电压才能工作,这个高电压一般由内部电荷泵电路产生.在传统Dickson电荷泵结构的基础上,提出一种改进的电荷泵结构.它首先将非重叠时钟的幅度加倍,然后用幅度加倍的时钟作为电荷泵的驱动时钟,取得了明显的升压效果.Hspice仿真结果表明,电源电压为1.4V时,6级二极管-电容升压单元就可以实现10.7674 V的输出电压.与传统的Dickson升压电路相比,改进型电荷泵的升压单元减少了4级,且其核心部分的面积减小了21％,功耗降低了40％(参考SMIC 0.35 μm CMOS工艺).     

一种高精度快速响应欠压锁定电路设计

针对传统欠压锁定(UVLO)电路结构复杂和响应速度慢的问题,设计了一种高精度的快速响应欠压锁定电路.该电路整体均由CMOS管组成,结构简单且易于实现.采用电流模控制技术,随电源电压呈二次方曲线变化的自偏置电流控制阈值电压的产生,有效提高了电路的响应速度.该欠压锁定电路基于0.18μm BCD工艺设计,并利用HSPICE进行仿真验证,当电源电压在0～5V区间变化时,输出电压翻转的上阈值门限为3.91 V,相应下阈值门限为3.82V,迟滞量为90 mV,温度在-40～125℃范围变化时,阈值门限电压容差仅为0.9μV,可实现输出电压的高精度转换,电路面积仅为15 μm×48μm.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

Charge Pump Architectures Based on Dynamic Gate Control of the Pass-Transistors

In this paper, we present two charge pump architectures for nonvolatile memories with dynamic biasing of the gate and the body voltages. By controlling the gate and the body voltage of each pass-transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the following with a negligible voltage drop and large conductivity. The charge pumps were fabricated in the ST 130-nm digital standard CMOS technology. Compared to conventional charge pumps, larger output voltage and better power efficiency are achieved still retaining a simple two-phase clocking scheme. Measurements performed on four-stage and eight-stage charge pumps are provided.      

一种用于AMOLED驱动的多模式高效电荷泵

设计了一种用于AMOLED驱动芯片的多模式高效低纹波电荷泵。该电荷泵通过模式选择,使输出电压可配置,实现多模式功能。针对电压建立和模式切换过程中电荷损耗的问题,利用初始化电路和电压检测电路来保证电荷泵中电荷单向传输,同时利用衬底选择开关来解决电荷泵的体效应问题,提高了电压转换效率。采用双边对称的泵电路结构,减小了输出电压纹波。采用UMC 80 nm CMOS工艺进行仿真。结果表明,负载电流为4 mA时,输出电压为8.4~17 V,四种工作模式下电压转换效率均在90%以上,电压纹波均小于1 mV。     

一种高精度低电源电压带隙基准源的设计

设计了一种可在低电源电压下工作,具有较高电源电压抑制比、低温度系数和低功耗的带隙基准电压源。电路基于对具有正负温度系数的两路电流加权求和的原理,对传统电路做出了改进。采用UMC 0.25 μmCMOS工艺模型,使用Hspice进行模拟,设计的基准源输出电压为900 mV,电源电压可降低到1.1 V,温度系数为8.1×10^-6/℃。     

基于电流镜积分的红外探测器读出电路设计

详细分析了电流镜积分(CMI)读出电路的工作原理、设计过程和CMI结构的噪声,并用CSMC 0.5μm CMOS工艺对所设计的电路进行仿真和版图设计,仿真结果表明CMI结构在电源电压为5 V,积分电容为2 pF时能提供一个较大的电荷存储能力(6.25x107个电子);在光生电流为50 pA时,探测器偏压稳定在3.615...     

A regulated charge pump with small ripple voltage and fast start-up

A regulated charge pump circuit is realized in a 3.3-V 0.13-/spl mu/m CMOS technology. The charge pump exploits an automatic pumping control scheme to provide small ripple output voltage and fast start-up by decoupling output ripple and start-up time. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an automatic pumping frequency control scheme. The former automatically adjusts the size of pumping driver to reduce ripple voltage according to output voltage. The latter changes the pumping period by controlling a voltage-controlled oscillator (VCO). The output frequency of the VCO varies from 400 kHz to 600 kHz by controlling the input bias voltage of the VCO. The prototype chip delivers regulated 4.5-V output voltage from a supply voltage of 3.3 V with a flying capacitor of 330 nF, while providing 30 mA of load current. The area is 0.25 mm/sup 2/ and the measured output ripple voltage is less than 33.8 mV with a 2-/spl mu/F load capacitor. The power efficiency is greater than 70% at the range of load current from 1 to 30 mA. An analytical model for ripple voltage and recovery time is proposed demonstrating a reasonable agreement with SPICE simulation results.     

一种无运放低压低功耗CMOS带隙基准电压源的设计

采用无运放电路结构,通过改进反馈环路和调整电阻的方法,设计了一种低电压低功耗的带隙基准电压源.相比传统有运放结构,电路芯片面积更小和具有更低的电流损耗,并且大部分电流损耗都用于产生输出电压.基于CSMC 0.5 μmCMOS工艺对所研制带隙基准电压源进行流片,测试结果表明,当电源电压大于0.85 V时,能够产生稳定的输...     

0.13μm BiCMOS低压差线性稳压器

设计了一种0.13μm BiCMOS低压差线性稳压器(LDO),包括BiCMOS误差放大器、带软启动的BiCMOS带隙基准源、"套筒式"共源-共栅补偿电路等。为了改善线性瞬态响应性能,在BiCMOS误差放大器的前级设置了动态电流偏置电路。由于所设计的BiCMOS带隙基准源对温度的敏感性较小,故能为LDO提供高精度的基准电压。对所设计的LDO进行了工艺流片。流片测试结果表明,该LDO可提供60 mA的输出电流且最小压差只有100 mV。测试同时验证了所设计LDO的负载和瞬态响应都得到改善:负载调整率为0.054 mV/mA,线性调整率为0.014%,而芯片面积约为0.094 mm2,因此特别适用于高精度、便携式片上电源系统。     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

一款高精度低功耗电压基准的设计与实现

设计了一款高输出电压情况下的高精度低功耗电压基准电路.电路采用了比例采样负反馈结构达到较高和可控的输出电压,并利用曲率补偿电路极大地减小了输出电压的温度系数.针对较宽输入电压范围内的超低线性调整率规格,给出了多级带隙级联的电路结构.针对功耗和超低负载调整率的问题,电路采用了基于运算放大器的限流模式和内置大尺寸横向扩散金属氧化物半导体(LDMOS)晶体管的设计.该电路在CSMC 0.25 μm高压BCD工艺条件下进行设计、仿真和流片,测试结果表明,该电压基准输出电压为3.3V,温度系数为19.4×10-6/℃,线性调整率为5.6 μV/V,负载调整率为23.3 μV/V,工作电流为45 μA.     

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE)circuit is introduced.The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly.In addition,a buffer with ultra-low output impedance is presented to improve line and load regulations.This design is fabricated by SMIC 0.18 μm CMOS technology.Experimental results show that,the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV.Moreover,the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.     

一种高效单相电源Ⅰ类线性音频功放的设计

采用SMIC0.18μm3.3V CMOS工艺,实现了单相电源Ⅰ类线性音频功放的设计。为了提高AB类功放的效率,设计了一种新型结构的Ⅰ类线性音频功放,并理论推导了它的效率。Ⅰ类音频放大器中的电源转换器能根据输入音频信号连续调节AB类功放的功率电源电压以减小功率管上的压降。为了使单相电源下PMOS和NMOS功率管功耗同时得到优化,设计了增益变化的信号处理电路。输出级采用桥式结构,并由三级运放构成以提高线性度。测试结果表明,该功放向8Ω阻性负载提供功率在小于270mW范围内时,总谐波失真与噪声之和小于0.45%,最大效率达到70%;功率在100mW范围内时,效率比AB类提高了一倍,且测试效率曲线与理论推导吻合。     

低压CMOS带隙电压基准源设计

在对传统典型CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈技术,提出了一种1-ppm/°C低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路设计。放大器输出用作电路中PMOS电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC0.35μmCMOS工艺实现,采用HSPICE进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。