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Wireless Networks - In this article, a novel ultra-high frequency radio frequency identification (UHF RFID) reader antenna is proposed and experimentally investigated. The proposed RFID antenna... 相似文献
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2.5 mm2 including pads. 相似文献
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A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads. 相似文献
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超高频射频识别系统具有存储容量大、读写速度快、识别距离远和可同时读写多个电子标签等特点,已经在众多领域得到了广泛的应用。为了满足市场需求,对超高频读写器的内部结构进行了研究并提出了一种基于ARM的超高频射频识别系统读写器的设计方案。从硬件和软件两个方面对读写器的设计进行了阐述,给出了读写器的设计结构、工作流程以及相关的软件流程图。实际应用结果表明,该读写器具有读写速度快、读写效率高、识别距离远等优点,可以满足市场需求。 相似文献
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Bidirectional radiated circularly polarised square-ring antenna for portable RFID reader 总被引:1,自引:0,他引:1
A novel single-layer, dual-fed technique for a bidirectional radiated circularly polarised square-ring antenna operated in the UHF band is presented. The two feed ports of the square-ring radiating element are placed in orthogonal directions and connected to a feeding network with a Wilkinson power divider in the same plane. Properly adjusting the size of the capacitive coupling groundplane results in good impedance matching and circularly polarised radiation, and a broad impedance bandwidth (S11 ⩽ -10 dB) of about 45.2% and a 3 dB axial-ratio bandwidth of about 8.7% were obtained. 相似文献
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RFID标签天线的性能直接影响到整个系统的性能.传统制作方法及偶极子结构使天线在尺寸、增益等重要指标上很难有所突破.依据所涉及的UHF RFID系统的设计参数要求和标签天线高性能、小尺寸的目标,提出了一种基于LTCC技术的新型片式天线结构.它由两层嵌入在LTCC基板中的金属线构成,平面尺寸仅为0.89 cm×1.018 cm.测试结果证明,天线性能达到设计要求.此外,该天线具有全向性好,性能稳定等优点.LTCC技术也为实现UHF RFID标签的全集成化奠定了基础. 相似文献
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A novel reader loop-type antenna for ultra-high-frequency (UHF) near-field radio frequency identification (RFID) applications is presented. This antenna, printed on a 0.8 mm-thick FR4 substrate with a diameter of 16 cm, is composed of four curved strips and four pairs of coupled stubs, and achieves a wide impedance bandwidth from 840 to 1300 MHz. The proposed structure can make large currents along the loop so that a strong and uniform magnetic field distribution is excited in the region around the antenna. Measurements show that the antenna operating with a commercial reader demonstrates good performance of tag identification with inductive coupling for near-field RFID applications. 相似文献
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针对符合ISO/IEC 18000-6B标准的UHF RFID读写器需要高效地解码FMO编码的基带信号,从而高效地识别标签返回信息的要求,提出了利用高速MCU分段多次同步、多次采样并结合IQ正文信号复合校验的解码方法对四通道零中频接收机解调出来的FMO基带信号进行解码.通过实验表明,该方法提高了UHF RFID读写器解... 相似文献
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自主知识产权RFTD标准系列报道(二)UHF RFID空口技术自主创新研究 总被引:1,自引:0,他引:1
杜江 《信息技术与标准化》2009,(11):57-60
在分析自主RFID标准必要性的基础上,介绍中兴通讯在RFID领域的自主创新,包括RFID产品研发历程、UHF RFID关键技术创新及自主空口协议,重点阐述了自主空口协议中物理层信道编码、物理层数据同步、多标签防碰撞、高效空口交互等关键技术。 相似文献
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设计了一种基于AS3992的手持式超高频RFID阅读器。阅读器的射频收发电路由AS3992内部集成的射频模拟前端和协议处理系统构成,基带控制由S3C2440建立的最小系统实现。对AS3992射频模块电路进行了介绍,针对天线设计了阻抗匹配电路,对S3C2440外围电路进行了设计,同时设计了Linux系统下各硬件的驱动程序以及应用程序,最后对设计的阅读器进行了测试分析。结果表明,阅读器能支持ISO/IEC 18000-6C协议,并且具备了可手持、发射频率可调、功能易扩展等特点,满足智能物联网市场的需求,有非常好的应用前景。 相似文献
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Modeling and analysis of far field power extraction circuits for passive UHF RF identification (RFID) applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied. 相似文献
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Modeling and analysis of far field power extraction circuits for passive UHF RF identification (RFID) applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear ap-proximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied. 相似文献
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Shi Wanggen Zhuang Yiqi Li Xiaoming Wang Xianghua Jin Zhao Wang Dan 《半导体学报》2009,30(4):045004-045004-4
A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed.This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption.By applying methods like system-level power management,global clock gating and low voltage implementation,the total power of the design is reduced to a few microwatts.In addition,an innovative way for the design of a true RNG is presented,which contributes to both low power and secure data transaction.The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows.The design fits different CMOS technologies and has been taped out using the 2P4M 0.35μm process of Chartered Semiconductor. 相似文献
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A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor. 相似文献