共查询到9条相似文献,搜索用时 15 毫秒
1.
Zhi-Qiang Lu Jian-Guo Ma Feng-Chang Lai 《Analog Integrated Circuits and Signal Processing》2006,49(1):27-30
A 900-MHz two-stage CMOS voltage controlled ring oscillator (VCRO) with quadrature output is presented. The circuit is designed
in a 0.18-um CMOS technology and operated on a 1.8-V supply voltage. The VCRO have a tuning range of 730 MHz to 1.43 GHz and
good tuning linearity. Between 0 V and 1.1 V of control voltage, the gain of VCRO is around −620 MHz/V. At 900 MHz, the phase
noise of the VCRO is −106.1 dBc/Hz at 600-KHz frequency offset with power consumption of 65.5 mW. 相似文献
2.
This paper proposes a novel phase-noise reduction technique for high performance voltage-controlled oscillator (VCO) using a cross-coupled series LC resonator, rather than parallel LC resonator. The proposed technique makes a time difference between the zero crossing point of the drain node voltages and that of the gate node voltages of the switching pair. By adding cross coupled PMOS loading, the drain voltages are made close to a rectangular shape, which makes an ideal on–off switching of the VCO. Since the current source contributes large portion of noise to the output, it is removed in the proposed VCO to further improve the noise performance. While the series connected inductor and capacitor enhances the fundamental frequency swing at the LC connection node, it gives a cleaner spectral purity output and suppresses the overall noise at the drain node of the cross-coupled switching cell. 相似文献
3.
4.
This paper presents a new design for a three-stage voltage-controlled differential ring oscillator embedded with a delay cell for a wide tuning range from 59 MHz to 2.96 GHz by adjusting the current level in the delay cell. The ring oscillator consists of a voltage-to-current converter, coder circuit, three-stage ring with delay cells, and current monitoring circuit to extend the tuning range of the proposed voltage-controlled oscillator. Each functional block has been designed for a minimum power consumption using the TSMC 0.18 μm CMOS technology. We simulate the performances of the proposed voltage-controlled oscillator in terms of phase noise, power consumption, tuning range, and gain. Our simulation results show that the proposed oscillator has the linear frequency–voltage characteristics over a wide tuning range. At each tuning range (mode), the calculated phase noise of the proposed ring oscillator at each tuning range (mode) was −87, −85, −81, and −79 dBc/Hz at a 1 MHz offset from the center frequency. The DC power of the proposed voltage-controlled oscillator consumed 0.86–3 mW under a 1.8 V supply voltage. 相似文献
5.
With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz. 相似文献
6.
Reliability analysis of MOS varactor in CMOS LC VCO 总被引:1,自引:0,他引:1
Yidong Liu 《Microelectronics Journal》2011,42(2):330-333
The paper investigates the reliability of MOS varactor tuned voltage-controlled oscillators (VCO). Due to the stress induced threshold voltage shift of the MOS varactor, the resonant tank degrades and the center frequency and phase noise of VCO deviate. The behavior is modeled and an adaptive body biasing scheme is proposed to make VCO resilient to reliability. In the mean time it does not degrade the VCO performance. An LC VCO at 24 GHz carrier frequency with adaptive body biasing is compared with VCO without such biasing design in PTM 65 nm technology. The ADS simulation results show that the biasing design helps improve the robustness of the VCO in resonant frequency. The design reduces the frequency sensitivity of VCO by 20% when subjected to threshold voltage degradation. 相似文献
7.
A wideband low-phase-noise LC voltage-controlled oscillator (VCO) with low VCO gain (Kvco) vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier. 相似文献
8.
Hwann-Kaeo Chiou Hsien-Jui Chen Hsien-Yuan Liao Shuw-Guann Lin Yin-Cheng Chang 《Microelectronics Journal》2008,39(12):1687-1692
A low phase noise with wide tuning range complementary LC cross-coupled voltage control oscillator (LC-VCO) using 0.18 μm CMOS technology is presented. This paper proposes a design formula for the choice of the value of varactor (ΔCvar) and band switch capacitor (Cs) for the binary-weighted band-switching LC tank which is convenient to determine the proper tuning constant for wideband, low-phase-noise operations. This general formula considers the ratio of frequency overlap (ov) and all the parasitic effects from band-switching capacitor array and transistors. The designed VCO using a 4-bit band-switching capacitor array demonstrates the operating frequencies from 4.166 to 5.537 GHz with an equivalent tuning bandwidth of 28.26%. The measured tuning range of all sub-bands is well agreed with that of the post-layout simulation results. The measured phase noise is −123.1 dBc/Hz at 1 MHz offset in the 5.2 GHz band. The calculated figure-of-merit (FoM) of this VCO was as high as −187 dB. When considering the tuning bandwidth the designed VCO obtains a FoM-bandwidth product of 52.83, which is much better than previously published works. 相似文献