Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Performance and optimisation of dual material gate short channel BULK MOSFETs for analogue/mixed signal applications

The challenge of analogue operation of CMOS devices and its parameters is a very important study for future technologies. In this article, the performance of dual material gate bulk MOSFETs for analogue/mixed signal applications is explored. Moreover, the optimisation of the device is done based on the variation of length and work-function difference of the two gate metals. The effect of drain induced barrier lowering in this structure is studied in detail. Moreover the different analogue parameters such as transconductance (g _m), output resistance (R _o) tuning for high performance of the device are also investigated by extensive simulations.     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (g_m), output conductance (g_d), Early Voltage (V_EA), Maximum Transducer Power Gain, cut-off frequency (f_T), and I_on/I_off ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable I_on of~31.8 μA/μm and saturation transconductance g_m of~68.2 μS with improved third order derivative of transconductance g_m3.     

A new two-dimensional C-V model for prediction of maximum frequency of oscillation (fmax) of deep submicron AlGaN/GaN HEMT for microwave and millimeter wave applications

An analytical two-dimensional capacitance-voltage model for AlGaN/GaN high electron mobility transistor (HEMTs) is developed, which is valid from a linear to saturation region. The gate source and gate drain capacitances are calculated for 120 nm gate length including the effects of fringing field capacitances. We obtain a cut-off frequency (f_T) of 120 GHz and maximum frequency of oscillations (f_max) of 160 GHz. The model is very useful for microwave circuit design and analysis. Additionally, these devices allow a high operating voltage V_DS, which is demonstrated in the present analysis. These results show an excellent agreement when compared with the experimental data.