A Mixed Signal Fuzzy Controller Using Current Mode Circuits

A mixed analog-digital fuzzy logic inference processor chip, designed in a 0.35-μm CMOS technology, is presented. The analog fuzzy engine is based on a novel current-mode CMOS circuit used for the implementation of fuzzy partition membership functions. The architecture consists of a 3 inputs—1 output analog fuzzy engine, internal digital registers to store the parameters of the fuzzy controller, and a digital subsystem that allows the programmability of the fuzzy controller via an I ² C interface. The architecture, circuits, and some Cadence Spectre simulations are presented.     

A mixed-signal array processor with early vision applications

Many early vision tasks require only 6 to 8 b of precision. For these applications, a special-purpose analog circuit is often a smaller, faster, and lower power solution than a general-purpose digital processor, but the analog chips lack the programmability of digital image processors. This paper presents a programmable mixed-signal array processor which combines the programmability of a digital processor with the small area and low power of an analog circuit. Each processor cell in the array utilizes a digitally programmable analog arithmetic unit with an accuracy of 1.3%. The analog arithmetic unit utilizes a unique circuit that combines a cyclic switched-capacitor analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to perform addition, subtraction, multiplication, and division, Each processor cell, fabricated in a 0.8-μm triple-metal CMOS process, operates at a speed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 μm by 270 μm of silicon area. An array of these processor cells performed an edge detection algorithm and a subpixel resolution algorithm     

基亏DSP的多路音／视频采集处理系统设计

采用TI公司的TMS320DM642型数字媒体数字信号处理器（DSP）设计多路音／视频采集处理系统，实现实时处理4路模拟视频和音频输入、1路模拟／数字视频和1路模拟音频信号输出的功能，该系统可适应PAL／NTSC标准复合视频CVBS或分量视频Y／C格式的模拟信号和标准麦克风或立体声音频模拟输入，具有PAL／NTSC标准S端子或数字RGB模拟／数字信号输出和标准立体声音频模拟输出。并给出软／硬件设计原理和电路。     

An audio amplifier providing up to 1 Watt in standard digital 90-nm CMOS

An audio amplifier in a standard 90-nm dual gate-oxide CMOS technology is designed for direct connection to the battery in a mobile phone. Special techniques have been applied to run it from a supply voltage of up to 5.5 V. The circuit does not require a dedicated supply voltage generator; it can be integrated on the same chip with the digital signal processor, and provides high output power, good power supply rejection, and good efficiency.     

Mixed analog-digital crossbar-based hardware implementation of sign–sign LMS adaptive filter

Recently announcement of a physical realization of a fundamental circuit element called memristor by researchers at Hewlett Packard (HP) has attracted so much interest worldwide. Combination of this newly found element with crossbar interconnect technology, opened a new field in designing configurable or programmable electronic systems which can have applications in signal processing and artificial intelligence. In this paper, based on the simple memristor crossbar structure, we will propose a new mixed analog-digital circuit as a hardware implementation of the sign–sign least mean square (LMS) adaptive filter algorithm. In this proposed hardware, any multiplication and addition is performed with infinite precision and there is no necessity for the quantization of the input signal. Since the coefficients of the filter are stored in the switches of the crossbar, they can remain unchanged theoretically for an infinite period of time.     

便携式智能油气检测仪设计

为了防备油气浓度超标造成的安全事故,研制了便携式智能油气检测仪。采用接触燃烧式气敏传感器进行油气检测,并增加补偿元件。用电桥电路作为测量电路,用双端输入方式连接电桥与运算放大器,对所采集的信号作放大、补偿处理。采用集成电路A/D芯片进行信号A/D转换,并在LCD数字显示屏上显示油气浓度值。设计报警电路,用C＋＋语言设计软件,采用单片机进行系统控制。气敏元件的误差补偿和数字化浓度检测有创新。该检测仪适用于石油、天燃汽等储运和使用场所。     

Ka-band analog front-end for software-defined direct conversion receiver

A six-port Ka-band front-end architecture based on direct conversion for a software-defined radio application is proposed in this paper. The direct conversion is accomplished using six-port technology. In order to demodulate various phase-shift-keying/quadrature-amplitude-modulation (PSK/QAM) modulated signals at a high bit rate, a new analog baseband circuit was specially designed according to the I/Q equations presented in the theoretical part. An experimental prototype has been fabricated and measured. Simulation and measurement results for binary PSK, quaternary PSK (QPSK), 8 PSK, 16 PSK, and 16 QAM modulated signals at a bit rate up to 40 Mb/s are presented to validate the proposed approach. A software-defined radio can be designed using the new front-end and only two analog-to-digital converters (ADCs) because the I/Q output signals are generated by analog means. Previous six-port receivers make use of four ADCs to read the six-port dc levels and require digital computations to generate the I/Q output signals. With the proposed approach, the load of the signal processor will therefore be reduced and the modulation speed can be significantly increased using the same digital signal processor.     

Design of vision measurement system of double optical paths with single CCD based on DSP

The design of vision measurement system of double optical paths with single CCD based on the digital signal processor （DSP） is presented. Using TMS320F2812 as the intelligent control unit, the CCD driving circuit, level conversion circuit and CCD output signal data acquisition and processing circuit are designed. By means of plane reflectors, the optical structure of the system is optimized, which reduces errors owing to tilt effect of the measured unit, improves measuring accuracy and makes the system more compact. Double optical paths signal data acquisition with single CCD is demonstrated. In addition, the improved resolution is enhanced up to sub-pixel level by the average polynomial interpolation algorithm.     

An Automatic Zeroing Circuit

A circuit to remove an offset from a signal is described. The circuit uses a simple digital memory to store the offset, and the output is the difference between this stored offset and the input signal. The drift is small, the bandwidth wide, and the input voltage may be obtained in digital form.     

一种功率型光耦合单片集成光电检测电路

针对功率型光电检测电路微弱光信号检测和功率输出的需求,研制了一种集成光电探测传感器和信号处理电路,且带功率驱动功能的单片光电检测电路.从理论上探讨了光电探测器的工艺兼容与系统噪声匹配,设计了专用的光电探测器以及适用于功率型光电集成电路(OEIC)的信号处理单元.采用B6035双极工艺,进行了版图设计和流片测试.测试结果表明,该电路的电源电压工作范围、静态功耗和传输延迟时间等综合性能优于同类型混合组装电路.     

FPGA realization of space-vector PWM control IC for three-phase PWMinverters

This paper presents a new circuit realization of the space-vector pulse-width modulation (SVPWM) strategy. An SVPWM control integrated circuit (IC) has been developed using state of-the-art field-programmable gate array (FPGA) technology. The proposed SVPWM control scheme can be realized using only a single FPGA (XC4010) from Xilinx, Inc. The output fundamental frequency can be adjusted from 0.094 to 1500 Hz. The pulse-width modulation (PWM) switching frequency can be set from 381 Hz to 48.84 kHz. The delay time for the PWM gating signals is adjustable. This SVPWM IC can also be included in the digital current control loop for stator current regulation. The designed SVPWM IC can be incorporated with a digital signal processor (DSP) to provide a simple and effective solution for high-performance AC drives. Simulation and experimental results are given to verify the implemented SVPWM control IC     

A Digital Controller Assisted Flexible Auto-tuning Method for Continuous-time Filters

A novel auto-tuning method for the integrated continuous-time filter is proposed in this paper. On the one hand, an off-chip digital controller is adopted here to decrease the on-chip hardware as well as to increase the efficiency and the flexibility of the auto-tuning strategy. As a result, both the calibration and the programmability of the cut-off frequency can be realized by software, meanwhile some non-idealities of the circuit can also be compensated by software. On the other hand, the on-chip auto-tuning circuit is designed based on the master-slave architecture, where a novel and simple master circuit is adopted with digital input and output interfaces, thus providing convenient connections for the controller without the ADC or DAC devices. With the PCB technology, a 6th-order active-RC filter with the proposed auto-tuning method is also implemented to verify the validity and the flexibility of this method.     

Algorithmic Measurement of Digital Instantaneous Frequency

This paper presents an algorithmic method for measuring the instantaneous frequency of a uniformly sampled FM signal. The measured parameter, termed digital instantaneous frequency, is defined in a manner similar to that used to describe frequency-modulated, continuous-time signals. The measurements are derived from an adaptive linear prediction spectral estimates. The proposed algorithm is utilized in the development of a digital processor for FM demodulation which operates on a uniformly sampled FM signal, and its output is a sampled sequence of the estimated demodulated message. The performance of the digital processor is demonstrated and compared with that of a conventional FM discriminator.     

D/A转换在System View环境下的仿真及硬件实现

针对模拟信号在传输介质中优于数字信号,而设计数模转换模块。首先用System View对DAC模块进了仿真。然后设计的D/A转换的硬件电路。通过设计了一个前置的串并转换电路,不仅可以实现8位并行数字信号的D/A转换,还可实现8位串口输入数字信号的D/A转换。在输出端,接入一个有源二阶低通滤波电路,使模拟输出更为平滑。达到了在实际范围内较低波形衰减的目的。     

多通道升降沿产生激光驱动器超窄脉冲新方法

应用于不同领域的超窄脉冲激光驱动器要求输入脉冲宽度极窄,并且大范围内可调。传统的模拟器件可调性差难以满足要求,数字器件例如专用集成电路(ASIC)尽管脉冲宽度可以实现超窄输出,但是大范围内可调不易满足,并且存在可扩展性差,价格昂贵等特点,同样不利于推广。现场可编程门阵列(FPGA)程控性好,因此在脉冲激光驱动器中的数字脉冲源得到了很好的应用,但是传统的计数方法只能实现脉宽为时钟周期倍数的脉冲输出,因此只能应用于对窄脉宽要求不高的情形。为解决上述问题,本文基于FPGA设计了一种应用于超窄脉冲激光驱动器,在50 MHz时钟频率下利用锁相环倍频成多个通道的基准时钟,并分别利用上升下降沿计数器进行计数,再经不同逻辑运算输出的数字脉冲产生方法。最终的数字电路可以产生脉宽2～50 ns,步长1 ns可调,重复频率1 Hz～1 MHz的数字脉冲信号。最后分析了在高精度锁相环等硬件条件满足的情况下,该方法可以实现亚纳秒脉宽和步长的数字脉冲信号输出,因此具备了很好的可拓展性和前景。     

基于DSP的数字预失真系统设计

为提高无线通信系统的通信质量与效率,提出一种基于DSP自适应数字预失真技术的系统设计。采用TI公司的低功耗、高性能数字信号处理器TMS320VC5502,有效提高了信号处理速度,减少了回路延时。根据信号的幅度,数控衰减器工作在不同的控制模式,以满足不同系统输出功率的要求。结果表明,该系统能有效改善功率放大器的线性度,并将功放的邻道功率比（ACPR）降低了10 dB左右。     

Integrated Circuit Biosensors Using Living Whole-Cell Bioreporters

A low-power CMOS bioluminescent bioreporter integrated circuit (BBIC) is designed and fabricated for use in electronic/biological chemical sensing. The bioreporters are placed on a CMOS integrated circuit (IC) that detects bioluminescence, performs signal processing and produces a digital output pulse with a frequency that is proportional to the concentration of the target substance. The digital output pulse that contains the sensor information can then be transmitted to a remote location either wirelessly or via a data cable. The basic building blocks of the integrated circuit are the microluminometer and the transmitter. The microluminometer includes an integrated photodetector and a signal processor and is housed in a rugged inexpensive package that can be used in many remote applications in hazardous environmental monitoring. The total power consumption of the entire signal processing circuitry including the photodiodes is 3 mW from a 3.3-V power supply. This is lowered by a factor of 3 when compared to previous versions of the BBIC. In addition, it also integrates all features of detection, processing and data transmission into one small element. The bioreporter typically contains the luxCDABE reporter genes. The close proximity of the bioreporter and the sensing element eliminates the need for complex instrumentation to channel light from the bioreporters to the microluminometer. This paper presents an integrated CMOS microluminometer realized in 0.35-mum CMOS process and optimized for the detection of low-level bioluminescence as part of the BBIC. A flow-through test system was designed to expose the BBIC system composed of the microluminometer and the bioreporter Pseudomonas fluorescens 5RL to salicylate for determination of analytical benchmark data. The results obtained from the experiment are currently being used to study enclosures and micro-environment configurations for field-deployable BBICs for environmental monitoring     

Mixed-signal design of a fully parallel fuzzy processor

The authors present a novel architecture for implementing general-purpose fuzzy chips which allows fully-parallel rule processing employing a reduced number of mixed-signal computing blocks and minimum-sized digital memories. The resulting fuzzy processor can interact directly with continuous sensors and actuators and the subsequent digital processing system     

Programmable discrete-time type I and type II FIR filter design on the memristor crossbar structure

A new method for effective realization of discrete-time type I and type II FIR filters on the memristor crossbar structure is developed in this paper. For this purpose, first the analog input signal (to be filtered using the discrete-time filter) is discretized using the classical switched-capacitor circuit and then all of the required delayed samples of this discrete-time signal are generated using the circuit designed for this purpose. Next, the weighted sum of these delayed samples of the original discrete-time signal (which forms the output of the FIR filter under consideration) is produced using the memristor crossbar structure. The proposed structure for FIR filter design is, compared to classical methods, advantageous in the way that it does not need any processors or A/D converter. Moreover, it is fully implemented using analog devices and consequently free of round-off error. Another related contribution of this paper is the circuit proposed for automatic tuning the memristance of the given memristor to the desired value with a high accuracy. Four numerical examples, including the application of the proposed FIR filter for demodulation of AM signals, are studied and HSPICE simulations are presented.     

信号测量处理器的模块化设计

阐述了数字设备模块化设计需要考虑的因素,介绍了应用超大规模可编程集成电路FP GA将过去采用多机箱、多印制板设计的信号测量处理设备集成为单板模块的设计实现方法。应用该方法实现的信号测量处理器具有多功能集成和硬件可重编程的特点,且有多种类型接口,可以广泛推广应用。