Current Mode, Voltage Mode, or Free Mode? A Few Sage Suggestions

Many claims have been made about the benefits of a current-mode (CM) approach to IC design. The term is used to draw attention to some kind of special dependence on currents as signals, often without a clear orientation to the broader field, referring instead to recent CM papers. Its use suggests a significant and valuable distinction over “conventional” solutions, perhaps in the hope that this perspective, with an element of novelty at the cell level, will influence circuit design in the stringent context of IC production. This paper asks: What factors unambiguously define a current-mode circuit, and formally differentiate it from standard realizations of some function? Can one point to any compelling, and in the most favorable cases unique, advantages? Are these cells clearly of general value, capable of widespread utility? These issues are examined from the critical viewpoint that no circuits carry the entire functional burden by the exclusive use of either currents or voltages, and very few fully exploit the specific, but narrow, benefits of CM concepts. Real-world product development invariably demands the vigilant and full embrace of what might be called the Free Mode perspective, but merely as a mnemonic, not a classification.     

Charging time of a high-voltage impulse generator

For design and operation, it is useful to know the charging behaviour of high-voltage impulse generators. The problem is one of finding the sum of the voltages along a uniform RC line as a function of time, for a step input. It is shown that the response is very nearly a simple exponential curve having a time constant (2/?)3 times the total RC product for the line.     

Fixed negative interface charges compromise organic ferroelectric field-effect transistors

Capacitance–voltage (C–V) and current–voltage measurements have been undertaken on metal-ferroelectric-semiconductor capacitors and ferroelectric field-effect transistors (FeFETs) using the ferroelectric polymer poly(vinylidenefluoride-trifluoroethylene) as the gate insulator and poly(3-hexylthiophene) as the active semiconductor. C–V measurements, voltage-dependence of gate currents and FeFET transfer characteristics all confirm that ferroelectric polarization is stable and only reverses when positive/negative coercive fields are exceeded for the first time. The apparent instability observed following the application of depletion voltages arises from the development of a negative interfacial charge which more than compensates the ferroelectric-induced shift, resulting in a permanent shift in threshold voltage to positive values. Application of successive bipolar voltage sweeps to a diode-connected FeFET show that significant remanent polarization is only induced in an unpoled device when the coercive field is exceeded during the first application of accumulation voltages. This initial polarization and its growth during subsequent bipolar voltage sweeps is accompanied by the accumulation of the fixed interfacial negative charges which cause the positive turn on voltages seen in C–V and transfer characteristics. The origin of the negative charge is ascribed either to layers of irreversible ferroelectric domains at the insulator surface or to the drift to the insulator-semiconductor interface of F^- ions produced electrolytically during the application of accumulation voltages.     

Extension of the common-mode range of bipolar input stages beyondthe supply rails of operational amplifiers and comparators

When the input voltage of an operational amplifier or comparator with a bipolar input stage exceeds the range of normal operation, the polarity of the output signal reverses and the input bias current increases to excessively large values. Saturation of the input transistors restricts the sensing of differential voltages to a common-mode (CM) range roughly between the positive and the negative supply rails. Input stage configurations that not only provide solutions to prevent the signal reversal and the excessive increase of input bias current, but also provide an extension of the CM range far beyond the supply rails, while the transconductance for differential input voltages remains constant, are described. Integrated implementations of the input stages realized a CM range reaching +15 V at a single supply voltage as low as 1 V, while the input bias current was limited to 6 μA     

A phase-noise reduction technique for RF CMOS voltage-controlled oscillator with a series LC resonator

This paper proposes a novel phase-noise reduction technique for high performance voltage-controlled oscillator (VCO) using a cross-coupled series LC resonator, rather than parallel LC resonator. The proposed technique makes a time difference between the zero crossing point of the drain node voltages and that of the gate node voltages of the switching pair. By adding cross coupled PMOS loading, the drain voltages are made close to a rectangular shape, which makes an ideal on–off switching of the VCO. Since the current source contributes large portion of noise to the output, it is removed in the proposed VCO to further improve the noise performance. While the series connected inductor and capacitor enhances the fundamental frequency swing at the LC connection node, it gives a cleaner spectral purity output and suppresses the overall noise at the drain node of the cross-coupled switching cell.     

Induced voltages in a low-voltage power installation network due tolightning electromagnetic fields: an experimental study

This paper presents experimental results on the induced common-mode (CM) voltages in a residential low-voltage power installation (LVPI) networks exposed to electromagnetic fields from lightning. The objective of this investigation was to find out the severity of induced voltages in a low voltage network due to direct coupling of the lightning electromagnetic fields with the network in the absence of transient overvoltages coming through the distribution lines. Flashes at a distance of about 25 km produced many induced-voltage pulses as large as 100 V, six such pulses in a time period of 0.4 ms in a negative CG flash, and 11 such pulses in a time period of 3 ms in a CC that immediately followed the ground flash     

A very high performance self-biased cascode current mirror for CMOS technology

This paper presents a novel high performance self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This circuit uses super cascode configuration to obtain high output impedance required for high performance of CM. Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM are carried out by Mentor Graphics Eldospice based on TSMC 0.18 μm CMOS technology, for input current range of 0–500 μA. A bandwidth of 2.26 GHz, input and output resistances of 679 Ω and 482 MΩ respectively, are obtained with a single supply voltage of ?1 V.     

The optimum fin width in p-MuGFETs with the consideration of NBTI and hot carrier degradation

Generally it is known that NBTI degradation increases with decrease of a channel width in p-MOSFETs but hot carrier degradation decreases. In this work, a guideline for the optimum fin width in p-MuGFETs is suggested with consideration of NBTI and hot carrier degradation. Using the device lifetime defined as the stress time necessary to reach ΔV_TH = 10 mV, the optimum fin widths have been extracted for different stress voltages and temperatures. When a fin width is narrower than the optimum fin width, the device lifetime is governed by the NBTI degradation. However, when fin width is wider than the optimum fin width, the device lifetime is dominantly governed by hot carrier degradation. The optimum fin width decreases with the increase of the stress voltage but it increases with the increase of the stress temperature.     

High-efficiency electrooptic Q-switching using slow risetime SCR-transformer drive

A transformer-driven electrooptic Q-switching technique and associated circuit are described which eliminate the requirement to switch high voltages and which greatly simplify circuitry. It is shown that this technique provides remarkably good lasing efficiency even when the transformer risetime is twice as slow as the laser pulse buildup time.     

The Effect of Discontinuities in a Multiconductor Line on Lightning-Induced Voltages

The effect of discontinuities in a transmission line on lightning-induced voltages is studied using a new field-to-line coupling model. For a shielding wire with an isolated grounding, it is shown that the mitigation of the induced voltages is due to the actuation of the localized grounding, when it is illuminated. It protects the line at its location and behind it, reducing the induced voltages by an amount that depends on the grounding resistance and the geometry of the conductors of the line, and also protects some points in front of it, but only within a certain “effective distance” that is dependent on the rise time of the induced voltages. For a periodically grounded shielding wire, it is shown that the reflection, at the grounding points, of the voltage reduction waves produced by the other groundings, produce oscillating induced overvoltages that are mainly confined in the line span in front of the strike. The effectiveness of the shielding wire can be enhanced if the insulation of the shielding wire is utilized as a protective gap. It is also shown that the effect of the ground resistivity is very important but is very different depending on the permittivity of the ground.      

Space-charge layer capacitance and offset voltage of an exponential-constant p-n junction

It is important to study an exponential-constant p-n junction because it gives a realistic approximation for many diffused p-n junction profiles. To calculate the space-charge layer capacitance for this junction we use an abrupt space-charge edge approximation with a correction which includes the effect of the mobile carriers at the edges of the space-charge region. In this approach the offset voltage v_off is used in place of the built-in potential as obtained from the depletion approximation. An analytical model for the space-charge region capacitance for an exponential-constant junction is developed. This model holds well for zero bias, for small forward voltages, and for reverse voltages. It shows good agreement when compared with the Chawla-Gummel model. It is simple and gives a direct relationship between the depletion capacitance and the applied voltage.     

栅压对LDMOS在瞬态大电流下工作的温度影响

研究 LDMOS在一次雪崩击穿后的大电流区,栅压对器件内部温度的影响.结果表明:温度随正栅压升高而升高,随负栅压升高而降低,并分析了有源区内电场强度、电流密度和功率密度随栅压的变化规律.从而证明,与LDMOS栅接地时相比,正栅压降低了器件的静电放电能力,而负栅压则提高了器件的静电放电能力.     

栅压对LDMOS在瞬态大电流下工作的温度影响

研究 LDMOS在一次雪崩击穿后的大电流区,栅压对器件内部温度的影响.结果表明:温度随正栅压升高而升高,随负栅压升高而降低,并分析了有源区内电场强度、电流密度和功率密度随栅压的变化规律.从而证明,与LDMOS栅接地时相比,正栅压降低了器件的静电放电能力,而负栅压则提高了器件的静电放电能力.     

Improving mobility and electrochemical stability of a water-gated polymer field-effect transistor

Water-gated organic transistors have attracted considerable attention in the field of biosensors, thanks to their capability of operating in the aqueous environment typical of biological systems at very low voltages (∼1 V). Some examples have been recently reported in the literature, employing different organic materials as the active semiconducting layer, ranging from small molecules to single crystals. Here we report on water-gated polymer-based organic-field effect devices using poly(2,5-bis(3-hexadecylthiophen-2-yl)thieno[3,2-b]thiophene) (pBTTT) as the active layer. Very promising electronic performances, in terms of mobility and operating voltages are obtained; notably, the charge carrier mobility is in the order of 0.08 cm²/V s, which is of the same order of magnitude of values reported for single-crystal based water-gated devices, and consistent with values reported for solid-state polymer dielectric transistors. Moreover, the pBTTT-based device shows improved electrochemical stability, as compared to previously reported polymer based water-gated devices. Importantly, good functioning of the device is demonstrated also when water is replaced by physiological-like solutions. Critical to the transistors operation, besides the good transport properties of the active material, is the key-role played by alkyl side chains and ordered morphology of the polymer at the interface with the liquid environment, which we highlight here for the first time. Our contribution overall provides a useful step towards the development of bio-organic sensors, with enhanced properties in terms of sensitivity and stability, and for a successful exploitation of organic based field effect transistors in biotic/abiotic interfaces.     

Low-voltage operational amplifier with rail-to-rail input and output ranges

An operational amplifier is described which can perform precision signal operations in nearly the full supply voltage range, event when this range is as low as 1.5 V totally. The untrimmed input offset voltage is typically 0.3 mV in an input common-mode (CM) voltage range which extends beyond both supply voltages for about 200 mV. The output voltage can reach each supply rail within 150 mV. A nested-loop frequency-compensation scheme yields a stable unity-gain bandwidth of 0.6 MHz while the low-frequency open-loop voltage gain is 110 dB. The op amp is integrated in a standard low-cost bipolar process and the chip measures 1.5/spl times/1.7 mm/SUP 2/.     

Optimal maintenance policies under different operational schedules

In the reliability literature, maintenance time is usually ignored during the optimization of maintenance policies. In some scenarios, costs due to system failures may vary with time, and the ignorance of maintenance time will lead to unrealistic results. This paper develops maintenance policies for such situations where the system under study operates iteratively at two successive states: up or down. The costs due to system failure at the up state consist of both business losses & maintenance costs, whereas those at the down state only include maintenance costs. We consider three models: Model A, B, and C: /spl middot/ Model A makes only corrective maintenance (CM). /spl middot/ Model B performs imperfect preventive maintenance (PM) sequentially, and CM. /spl middot/ Model C executes PM periodically, and CM; this PM can restore the system as good as the state just after the latest CM. The CM in this paper is imperfect repair. Finally, the impact of these maintenance policies is illustrated through numerical examples.     

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application

This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. The cell libraries come in fixed threshold—high V_th for good standby power and low V_th for high speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.     

The Contention Behavior of DOCSIS in CATV Networks

In this paper, we study the contention behavior of DOCSIS in cable TV networks. Specifically, we focus on the behavior of TCP over DOCSIS. We determine the expected access delay for TCP transmissions in CATV networks. The access delay here is defined as the interval between the time when a data packet arrives at a cable modem (CM) and the time when that packet is successfully sent by the CM. The analytical model is comprised of two parts. The first part is to calculate the probability that a CM sends a request in a randomly selected minislot, and the second part is to derive the expected access delay based on the probability derived in the first part. The accuracy of the analytical model is validated by simulations. The results show that our analytical model can accurately model the contention behavior of DOCSIS in CATV networks.     

A prognostic method for predicting failure of dc/dc converter

The failure of dc/dc converters can directly result in electronic systems working unconventionally or significant downtime. To pre-determine time to failure and generate substantial safety and cost benefits, it is necessary to assess the extent of deviation of dc/dc converters from its expected state of health in real time and predict time to failure in advance. This paper presents a novel prognostic method for predicting the time to failure of dc/dc converters. The process involves identifying precursor parameters, determining prognostic of failure, and determining a criterion for predicting time to failure. The output voltage is used as a precursor parameter and directly monitored when the converter with a given load periodically operates at different temperature stresses. The phenomenon that the differences of output voltages collected at different temperature stresses begin to increase with a large (or small) fluctuation is detected in collected output voltages. This phenomenon is identified as a prognostic of failure. A percentage of the initial difference is used as the criterion for predicting time to failure. A case study is given to illustrate the procedure that how to monitor output voltages, detect prognostic and predict time to failure. The results show the health state could be assessed in real time and the time to failure could be predicted in advance. Furthermore, the deviation of the predicted time to failure from the actual time to failure could meet the demand of a considered acceptable range in engineering practice.     

Current saturation effect for pentacene-based static induction transistor under negative drain-source and gate voltages

Usually, the drain-source current (I_DS) increases with positive drain-source voltage (V_DS) for pentacene-based organic static induction transistor (OSIT) ITO(Source)/Pentacene/Al(Gate)/Pentacene/Au(Drain) and it shows an inherent rectifying property under negative gate voltages (V_G), i.e. the slope of I_DS vs. V_DS curve increases with V_DS but without any current saturation effect. In this paper, we investigated the electrical characteristics of pentacene-based OSIT ITO/Pentacene(80 nm)/Al(15 nm)/Pentacene(80 nm)/Au under negative V_DS and V_G, and found that I_DS changed from rectifying property to saturation effect when the magnitude of negative V_DS was increased from 0 V to −6 V under negative V_G, and the turn-on voltage (V_ON) moved to larger negative voltages when the magnitude of negative V_G increased and the movement step of V_ON gets smaller after keeping the device for a long time, and the possible mechanisms for such a kind of current modulation were discussed.