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1.
Jingye Sun Shengxi Diao Guangtao Feng Fujiang Lin 《Analog Integrated Circuits and Signal Processing》2014,80(2):163-172
A 0.5–2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S11 < ?10 dB in the 0.5–2.5 GHz band. The noise figure (NF) is 3.9–5.0 dB and the IIP3 is 3.1–3.6 dBm. The power consumption is only 910 uW. 相似文献
2.
3.1~10.6GHz超宽带低噪声放大器的设计 总被引:1,自引:0,他引:1
基于SIMC0.18μmRFCMOS工艺技术,设计了可用于3.1—10.6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器(LNA)。该LNA采用三级结构:第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明:在电源电压为1.8v的条件下,所设计的LNA在3.1~10.6GHz的频带范围内增益(521)为20dB左右,具有很好的增益平坦性f±0.4dB),回波损耗S11、S22均小于-10dB,噪声系数为4.5dB左右,IIP3为-5dBm,PIdB为0dBm。 相似文献
3.
4.
Hsin-Ying Liang Cheng-Ying Yang Kuang-Hao Lin Chia-Hsin Cheng 《Wireless Personal Communications》2016,86(3):1359-1376
A new ultra-wideband common gate low noise amplifier (LNA) for 3–6 GHz WLAN and WPAN applications is presented in which a current reused noise canceling structure utilized in the first stage not only provides a suitable noise performance, but also enhances the linearity characteristics of the LNA in a power efficient manner needed by WLAN/WPAN applications. The overall structure of the proposed LNA, consisting of three stages, namely input matching common gate stage with noise canceling, gain stage, and buffer one, is designed, laid out, and analyzed in 0.18 µm RF CMOS process. The LNA has a noise figure of 3.5–3.6 dB, a high and flat power gain of 20.27 ± 0.13 dB, and input and output losses of better than ?11 and ?14 dB, respectively, over the entire frequency band of 3–5 GHz, while these parameters are 3.5 dB, 20.75 ± 0.25 dB, ?15 and ?9 dB for the frequency band of 5–6 GHz, respectively. IIP2 and IIP3 of the proposed topology are equal to 25.9 and ?1.85 dBm, respectively, at 4 GHz frequency. The proposed LNA has 15.3 mW power dissipation from a 1.8 V supply. 相似文献
5.
Wei-Hung Chen Gang Liu Zdravko B. Niknejad A.M. 《Solid-State Circuits, IEEE Journal of》2008,43(5):1164-1176
A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent cancellation of the intrinsic third-order distortion from individual stages is exhibited with the common-gate and common-source cascade. The LNA is then limited by the second-order interaction between the common source and common gate stages, which is common in all cascade amplifiers. Further removal of this third-order distortion is achieved by incorporating a second-order-distortion-free circuit technique in the common gate stage. Implemented in 0.13 m CMOS technology, this LNA achieved 16 dBm in both the 900 MHz and 2 GHz bands. Measurements demonstrate that the LNA has a minimum internal gain of 14.5 dB, noise figure of 2.6 dB from 800 MHz to 2.1GHz while drawing 11.6 mA from 1.5 V supply voltage. 相似文献
6.
低噪声放大器是超宽带接收机系统中最重要的模块之一,设计了一种可应用于3.1~5.2GHz频段超宽带可变增益低噪声放大器。电路输入级采用共栅结构实现超宽带输入匹配,并引入电流舵结构实现了放大器的可变增益。仿真基于TSMC 0.18μm RF CMOS工艺。结果表明,在全频段电路的最大功率增益为10.5dB,增益平坦度小于0.5dB,噪声系数小于5dB,输入反射系数低于-15dB,在1.8V电源电压下,功耗为9mW。因此,该电路能够在低功耗超宽带射频接收机系统中应用。 相似文献
7.
This paper presents an inductorless complementary-noise-canceling LNA(CNCLNA) for TV tuners.The CNCLNA exploits single-to-differential topology,which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure.Linearity is also enhanced by employing a multiple gated transistors technique.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed CNCLNA achieves 13.5-16 dB voltage gain from 50 to 860 MHz,... 相似文献
8.
Ke-Hou Chen Jian-Hao Lu Bo-Jiun Chen Shen-Iuan Liu 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(3):217-221
A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm2 相似文献
9.
基于130 nm CMOS工艺,设计了工作于K波段的双平衡下变频混频器。在传统吉尔伯特单元基础上采用电流复用注入结构,减小了开关级的偏置电流,提升了开关性能。在开关级源端引入谐振电感,消除了开关共源节点处的寄生电容,抑制了射频信号的泄露,提高了增益,减小了噪声。仿真结果表明,输入射频信号为24 GHz,本振信号为24.5 GHz,本振输入功率为-3 dBm时,该混频器的转换增益为25.8 dB,单边带噪声系数为6.4 dB,输入3阶互调截点为-8.6 dBm。 相似文献
10.
设计了一个基于TSMC 0.18 μm CMOS工艺的2.45 GHz全差分CMOS低噪声放大器.根据电路结构特点,采用图解法对LNA进行功耗约束下的噪声优化,以选取最优的晶体管栅宽;设计了仅消耗15 μA电流的偏置电路;采用在输入级增加电容的方法,在改善输入匹配网络特性的同时,解决了栅极电感的集成问题.仿真结果表明:LNA噪声系数为1.96 dB,功率增益S_(21)超过20 dB,输入反射系数S_(11)和输出反射系数S_(22)分别小于-30 dB和-20 dB,反向功率增益S_(12)小于-30 dB,1 dB压缩点和三阶互调输入点IIP3分别达到-17.1 dBm和-2.55 dBm,整个电路在1.8 V电源下功耗为22.4 mW. 相似文献
11.
Wen-Lin Chen Sheng-Fuh Chang Guo-Wei Huang Yuh-Sheng Jean Ta-Hsun Yeh 《Microwave and Wireless Components Letters, IEEE》2007,17(10):718-720
A Ku-band CMOS low-noise amplifier (LNA) with high interference-rejection (IR), wide gain control range, and low dc power consumption is presented. The LNA consists of two common-gate metal-oxide-semiconductor field-effect transistors interconnected with an interstage parallel tank for the IR. The stacked common-gate stages share the same dc bias current to reduce power consumption and have controllable gain by changing this dc current. The implemented 0.13 mum CMOS LNA achieves measured power gain of 10.8 dB, noise figure of 4.2 dB, output P1 dB of -4.3 dBm at 15 GHz, while rejecting interference down to a 38.5 dB level. The gain control range is 23.3 dB by varying the gate voltage from 0.2 to 1.2 V. The LNA consumes only 4 mA from a 1.3-V supply. 相似文献
12.
A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads. 相似文献
13.
A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2. 相似文献
14.
Seong-Sik Song Dong-Gu Im Hong-Teuk Kim Kwyro Lee 《Microwave and Wireless Components Letters, IEEE》2008,18(2):118-120
A differential wideband low-noise amplifier (LNA) based on the current amplification scheme is presented for digital TV tuners. In order to highly improve the linearity and exploit the noise cancellation, a common-gate stage with positive current feedback is integrated in parallel with a common-source stage using the current mirror amplifier. The proposed 0.18-mum CMOS LNA exhibits a power gain of 20.5 dB, an IIP3 of 2.7 dBm, an IIP2 of 43 dBm, and an average noise figure of 3.3 dB with 32.4 mW power consumption at a 1.8-V power supply and 0.12 mm2 area. 相似文献
15.
提出了一种多频带低噪声放大器的设计方法,可用于集成多个频段于一部终端的通讯设备.它不同于以往的电路结构,而是由共栅极作为输入,与一个共源极MOS管构成两级放大器,并通过使用2 bit的控制信号控制电路中的MOS开关,以调节电路工作在900 MHz、1.7 GHz和2.4 GHz等三个不同的频带.电路使用先进的90nm工艺库进行仿真,结果显示各频带的增益均大于16 dB,噪声系数小于1.7 dB,三阶交调点IIP_3和1 dB增益压缩点分别大于-2.5 dBm和-15.5 dBm,电路同时具备了扩展并包含更多频带的能力. 相似文献
16.
Bruccoleri F. Klumperink E.A.M. Nauta B. 《Solid-State Circuits, IEEE Journal of》2001,36(7):1032-1040
This paper presents a methodology that systematically generates all 2-MOS-transistor wide-band amplifiers, assuming that MOSFET is exploited as a voltage-controlled current source. This leads to new circuits. Their gain and noise factor have been compared to well-known wide-band amplifiers. One of the new circuits appears to have a relatively low noise factor, which is also gain independent. Based on this new circuit, a 50-900 MHz variable-gain wide-band LNA has been designed in 0.35-μm CMOS. Measurements show a noise figure between 4.3 and 4.9 dB for gains from 6 to 11 dB. These values are more than 2 dB lower than the noise figure of the wide-band common-gate LNA for the same input matching, power consumption, and voltage gain. IIP2 and IIP3 are better than 23.5 and 14.5 dBm, respectively, while the LNA drains only 1.5 mA at 3.3 V 相似文献
17.
采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。 相似文献
18.
A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner 总被引:1,自引:0,他引:1
《Solid-State Circuits, IEEE Journal of》2009,44(3):686-698
19.
A millimeter‐wave (mm‐wave) high‐linear low‐noise amplifier (LNA) is presented using a 0.18 µm standard CMOS process. To improve the linearity of mm‐wave LNAs, we adopted the multiple‐gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate‐source bias at the last stage of LNAs, third‐order input intercept point (IIP3) and 1‐dB gain compression point (P1dB) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3. 相似文献